Use with MSP430 USI port ADS8361
Foreword ADS8361 A sampling rate is 16 analog to digital converter device of double-channel (ADC) of 500kSPS ,This converter has 4 the whole differentiating incoming channels, a pairwise pair, in order to realize the synchronous high-speed acquisition of signal. The input end to sample the hold amplifier is the whole differentiating, in addition, the input end of ADC keeps as the whole differentiating. This makes this ADC have remarkable common mode inhibitory potencies: It is 80dB in 50kHz, this is very important under the environment of high noise. MSP430 devices such as new MSP430F2013,etc. have common serial interface (USI) ,Therefore can be used in very simple and direct interface, this interface does not need to " bond logic " And there are few required software expenses. Some employ the requirement to realize accurate timing to the passway of synchronous data acquisition, we can obtain the required systematic result with this kind of interface at this moment. Hardware ADS8361EVMADS8361 It is the instrument of Dezhou (TI) Bunch that put out do the intersection of ADC and the intersection of electric machine control and the intersection of product series and product. EVM has offered the relevant platform, in order to demonstrate the function of ADS8361 ADC when cooperating with different TI DSP and microcontroller, and employed and offered and deposited and withdrawn all simulation and digital signal function conveniently to the made-to-order final user.
The hardware imterface structure chart eZ430-F2013 developing instrument eZ430-F2013 of Fig. 1 is the intact MSP430 developing instrument, including assessing MSP430F2013 all required software and hardware. We store excellently and offer this hardware with USB facilitated. EZ430-F2013 adopts embedded work bench IAR to integrate and develop the environment (IDE) ,In order to offer the intact simulated function, this device offers two kinds of options of independent system design and detachable goal board, in order to integrate in the existing design. More details, please visit: www.ti.com/ez430. The hardware imterface connects requiring and adopting three simple line interfaces (see Table 1) the most low of eZ430-F2013 and ADS8361EVM . Hardware connection is shown as Fig. 1. CLOCK of ADS8361, (RD + CONVST) Connect with Serial Data A pin to SCLK, MOSI and MISO pin of USI port separately. chip select (CS) The pin is earthed, because only put one ADC on the port. If connect the multiple device on the bus line, then GPIO that the chip select pin can be used on MSP430 device controls. Software interface MSP430 All software adopt IAR embedded to last platform (Kickstart edition) Write and compile. This software is a charge free edition of IDE, and here www.ti.com/ez430 The tools of websites are supported (TOOL SUPPORT) Some download. You can also ask to get the code used in examples. USI sets up USI module to offer the basic function of a synchronous serial Communication scheme of support. USI has built-in hardware functions, thus has simplified the implementation of SPI communication. In addition, USI module also has look-at-me functions, can further reduce the expenses of the software.
The intact single-channel switching cycle USI of Fig. 2 controls 0 and 1 (USICTL0 and USICTL1) depositing device Set up the elementary operation of the serial interface. Through setting up 3 in USICTL0, 5, 6 and 7, can dispose ports under SPI dominant mode. In addition, it can set up USI counter to cut off in USICTL1, thus realize SPI Communication effectively with the minimum software expenses. The polarity, signal source and speed of the serial clock can all be through setting up USI clock control depositing device (USICKCTL) Controlled. In terms of this text, clock polarity is set as zero (keep for being low) ,The clock source is SMCLK, the frequency demultiplication coefficient is one. Bit clock and shift register dispose and realize control in USI port, is counted the depositing device (USICNT) by USI location Location arrangement determine. There are 5 USICNT registers, can offer and reach cycle of 32 SCLKs more each time. If USICNT has for 0