On my Nova 1200, both the Cassette I/O board and the CPU board, were having issues passing serial tests. The /DS5 signal had incorrect logic levels, so I swapped some gates there and solved that problem.
Then the big problem, which took alot of work to diagnose and fix is specific to the CPU board. Using the Nova 1200 Logic Test tape (as in a virtual paper tape), tests were performed but no clear answer was forthcoming. It was failing, but the serial output messages weren't working right to tell us what failed, or now. I single-stepped through the program until we hit a test that didn't pass: the auto-incrementing addresses.
On a Nova, addresses 00020 thru 00027 auto-increment values when accessed. Meanwhile, addresses 00030 thru 00037 auto-decrement values when accessed. These functions worked, but unfortunately they were being activated on addresses 00120 thru 00137 which is not right at all.
It took days of tests, writing our own testing routines, and lots of oscilloscope captures before it was finally found. The N8859A quad-input NAND gate that is part of the address decode logic had started ignoring the /MBO13 and /MBO14 signals, meaning it was decoding incorrectly. That part has been replaced with a 74LS20 (despite technically requiring a 7440, Fairchild 9009, or the aforementioned Signetics part, which has no datasheet) -- it's fine. So, that problem finally got solved, but it was a pain because it's only using a single 4-input NAND gate to decode a 16-bit value for a 15-bit address. DG pulled this off by cycling through one nibble of the instruction at a time, synced with the four Processor Time Groups (PTGs).
See those cyan and magenta traces? When those go low, they should trigger the blue trace at the bottom to go high. There it is.
Anyway, that took alot to figure out, and it still doesn't work completely yet, but that's like 3 to 5 problems fixed in the span of a week, so I'd say that's pretty good progress.
