Glance of Intel's New Features on Year 2008 Processors
Intel Common System Interface (CSI)
Intel is ready to announce a new chip technology that is called "Common System Interface". The approach is barely resemblance to recent HyperTransport technology, and successful applauded by Advanced Micro Devices.
If market trends to set microprocessor be a brain of server, then Intel's newly Common System Interface (CSI) would be its nervous facility. It provides a revolutionized method for processors to communicate with each other and with the rest of a computer. This competitive technology is scheduled to release on the next generation of Itanium processors (codenamed Tukwila) in 2008, and for the desktop processors, we will expect it possibly reveal in 2009.
Besides CSI, Intel is also planning to release an integrated memory controller, which is housed on the main microprocessor rather than on a separate co-chip or co-processor. This design will speed up the most memory performance and so coincide with the new communications system, the industry expects. According to the Intel current roadmap diagram, based on FB-DIMM, at around the same time that it will release its peculiar CSI platform.
As Intel's promise that the microprocessors on CSI system will be connected collectively through fast point-to-point data busses with transfer speeds up to 6.4 Gigatransfers per second, quit faster than speed of 5.2 Gigatransfers per second on AMD's "Torrenza Platforms".
While other chip manufactures are working on 65nm processors, the chip leading pioneer, Intel has started developing “Penryn” 45nm micro-chips, prototypes of computer processors using new highly techniques that that further shrink circuitry, making the chips size smaller, run faster, and less power.
Intel “Penryn” micro-chip will go into initial production during the third season of 2007, with the magnitude of its processors being fabbed at 45nm around 2008. The Penryn architecture does not far from the prior design, respectively it heirs to present 65nm Core 2 Duo or Core 2 Quad micro-processors. Momentarily, the Dual Core “Wolfadle” and the Quad Core “Yorkfield” will be one of the stunned powerful brains inside of Intel’s micro-chip family.
Discover the new features, Penryn will extend the current core 2 architecture, it’s expected to play host to the fourth set of “Streaming SIMD Extensions (SSE), a further forty-eight instructions designed to improve the ability in micro-processor, which help to handle multimedia applications; Penryn will also provide two further instructions dubbed by Intel “application-targeted accelerators”. Super shuffle engine is another new feature being tossed around, which is the process of properly disposing user’s data in a compiler.
The benefit from this technology is that it cuts off the various processing in half, and there is no software needed in this change. Moreover, if users suppose to anticipate a larger space to store the short common data, Penryn micro-chips will contain a whopping 12MB of second level cache on a desktop model for hasten each of tasks, and the clock speed humbly start from 3GHz. How about the CPU bandwidth? 1600MHz should not be a dream as good as you wish.
Penryn will be also a key part of “Montevina”, Intel’s generation of Centrino mobile platform. Montevina’s likely on stage in the first season of 2008, while AMD is starting to roll out its own 45nm micro-processors. As the same cadence inside the CPU, Montevina boot up the FSB from 800MHz to 1066MHz with up to 6MB cache size in L2.
Deep Power Down Technology (C6)
The new power state in Penryn micro-architectures, tentatively called “Deep Down Power State”. There are five different C-states beside this function, including new of C0 being the computer at the normal state. C1, C3, and C4 fully kindle the various portions of the central processor in order to save the power usage while in each states.
Deep down comes closest to C4 which turns off both core clocks, meanwhile, it PLL and flushes the caches for preparing next quick response. But new design instead, deep down (C6) turns off the caches entirely, which provide the efficiency to reduce the core voltage, or even lower. When compare to C4 and C6 (deep down) capacity, C6 uses about a glorious 300% less power.
Looking beyond Penryn, there will be an inauguration in late 2008 for welcome advanced micro-architecture chip to the IT world. The next generation of “Nehalem” will offer 8 cores with memory controller and graphic capabilities in one unit. Amazing dynamically managed cores, threads, large cache, interfaces, and less power usage as well as simultaneous multi-threading, that would be a great banquet we look forward.
Intel is having 2 sockets as new Nehalem implement for the next generation in 2008, Socket B and Socket H will be plan on road. As far as we know, Nehalem is based on 45nm, and there would be some inspiring movements on this change, the new interconnect technology such as CSI (Common System Interface) and IMC (Integrated Memory Controller).
Socket B will equivalent of LGA1366, and Socket H will equal to LGA715; both sockets will support DDR3 from 1066MHz to 1600MHz memories, it is likely identical feature with AMD’s socket AM3 at the same time. For some reasons, the Socket B has more contact pads than Socket H, due to the LGA1366 processor has IMC built in, but another Nehalem based LGA715 CPUs would not have this new act respectively.
~ Alex Ling, 04-15-2007 ~
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