Leveraging SerDes Design Flows for IBIS-AMI Model Development
This webinar showcases a new workflow that has been developed jointly between MathWorks and SiSoft, which enables semiconductor companies to reuse their SerDes designs directly for IBIS-AMI model creation, simulation, and validation.
Using Simulink for the design and simulation of SerDes architectures
Creating AMI models directly from SerDes designs using C Code Generation and compilation to DLLs
Simulation and validation of IBIS-AMI models in SiSoft Quantum Channel Designer (QCD)
 A SerDes Balancing Act: Co-Optimizing TX and RX Settings to Maximize Margin
Increasing complexity in SerDes Tx and Rx designs requires trading off Tx and Rx equalization to maximize receiver eye margin. This involves trading off ISI and amplitude while choosing what equalization to apply at the Tx and Rx. This webinar presents co-optimization results for various channel types: lossy, ISI-dominated, industry-reference and hypothetical. Results presented are based on SiSoft's OptimEye
technology, which makes advanced co-optimization accessible to anyone working with serial links.
Examining S-Parameters: Look Before You Leap
S-parameter files used for signal integrity simulations come from multiple sources and have various levels of quality. Unfortunately, s-parameter issues often go undetected and, while the models still run in simulations, they can produce misleading results. To combat this, SiSoft’s Quantum Channel Designer (QCD) S-Parameter Checklist provides a quick, repeatable, and efficient method for S-parameter evaluation. During this webinar, participants will become better versed in S-parameter terminology, model development, and quality verification.
Simulating Large Systems with Thousands of Serial Links
SiSoft co-presented this DesignCon 2012 paper with Sergio Camerlo, an engineering director with Ericsson Silicon Valley (ESV) and Donald Telian of SiGuys. The paper discussed in this webast details the creation of a fully populated virtual system model generated through the use of
Virtual Prototype Analysis (VPA)
that can be used to perform many of the tests that would normally require a physical prototype. While not long ago systems had only several serial links, it’s now becoming common for systems to include hundreds – and even thousands – of such links. This paper describes the development and analysis of a large system with thousands of serial links. Due to the system’s size and complexity, the design team invested in a multi-year effort to build and qualify a virtual environment capable of both verifying connectivity and simulating any and all of the channels. Problematic channels with incomplete system-level connections, poor eye openings, or high BER are quickly identified. Performance limiters such as inherent discontinuities (and their associated resonances), and Tx/Rx equalization imbalance are found and examined in detail. The virtual system is also used to guide design choices such as layer stacking, via construction, back-drilling, and trace/connector impedances. Processes to optimize and select equalization choices are also described.  Link behavior can be extensively characterized and optimized before prototypes are built. The use of a virtual system model supports a 48 hour turnaround from PCB layout changes to updated results, versus a turn time of weeks for a physical prototype. Â
Multi-Gigabit Design with Xilinx IBIS-AMI Models
 Next generation communications, networking, and consumer electronics products are replacing high-speed parallel interfaces with multi-gigabit serial links as the primary means of moving data within a system. Conventional signal integrity and timing analysis won’t work for these links, which require analyzing millions of bits worth of behavior to reliably determine how jitter, noise and crosstalk affect link operating margins. The IBIS-AMI modeling specification enables standardized, interoperable simulation of SerDes PHYs at the high levels of simulation performance and accuracy needed to correctly predict the behavior of serial links. This webinar highlights how IBIS-AMI based simulation will enable you to increase design reliability while reducing engineering design time.
Using SiSoft’s Quantum Channel Designer software and IBIS-AMI models, systems designers can experiment with different combinations of channel lengths, connectors, via designs and Transmit / Receive equalization to quickly determine which configurations provide adequate operating margin and which don't. Pre- and post-layout simulation with Quantum Channel Designer allows designers to validate designs and reduce time to market while increasing confidence in their design's reliability and manufacturability. This complimentary webinar focuses on the following topics:
Xilinx IBIS-AMI simulation models for Virtex®-5, Virtex®-6 and Spartan®-6
Predicting serial link operating margins using simulation
Co-optimizing your channel design and SerDes configuration
Assessing the impact of jitter, noise & crosstalk
Xilinx IBIS-AMI Design Kits for SiSoft’s Quantum Channel Designer
Introductory videos for the Xilinx Virtex-5 IBIS-AMI Design Kits may be viewed in SiSoft eLearning:
View The Xilinx Virtex-5 Design Kit Videos
Vias Minus the Mystery - Understanding the Physics Behind Via Behavior
For many years, our understanding of the high frequency electrical behavior of vias in PC boards and packages has been at best incomplete, and more recently vias have been portrayed as the exclusive province of experts running 3D field solver programs. The fundamental problem is that there has not been any explanation of the physics of vias that would enable engineers to visualize the currents and fields, and therefore exercise engineering judgment in the design of vias. While the increasing data rates of high-speed serial channels makes it more important than ever to fully understand the electrical behavior of vias, we do now have an explanation for the physics of vias which is suitable for engineering use. A very simple experiment, for which closed form solutions to Maxwell’s equations match measured data and field solver results, demonstrates that the ground return path for a via can be explained in terms of radial TEM waves propagating between pairs of ground planes. Furthermore, this explanation can be extended to explain the interaction between vias. This webinar presents measured data, matching theoretical calculations, field solver results, and basic physical reasoning which demonstrates the role of radial TEM waves in the electrical behavior of vias. Additional measured data and the concept of radial TEM waves is then used to explain how vias interact. The result is a small number of engineering approximations which are sufficient to make most engineering decisions concerning vias.This complimentary webinar focuses on the following topics:
An explanation of the physics of vias as well as the interaction between vias
How to use the physical explanation of vias described here to enhance engineering judgment in the design of vias
Measured Data, Matching Theoretical Calculations, Matching Field Solver results, and Basic Physical Reasoning which demonstrate the role of radial TEM waves in the electrical behavior of vias
Presentation of a small number of engineering approximations sufficient to make most engineering decisions concerning vias
6.25 Gbps and Beyond - Serial Link Analysis & Optimization
As serial link speeds increase beyond 6.25 Gbps, most channels incur enough loss to close the signal eye at the receiver input and require active receiver equalization to recover a usable signal. This renders traditional lab measurements obsolete, as the sampled signal is no longer physically accessible. Simulation can be used to model the effect of transmit/receive equalization and predict a design’s operating margin. Unfortunately, traditional simulation techniques don't work for high speed serial links, either. Accurate prediction of Bit-Error Rate (BER) requires simulating billions of bits worth of data, which isn't possible with traditional signal integrity tools. Effective serial link analysis requires combining frequency-domain, time-domain and statistical techniques with accurate modeling of SerDes equalization and clock recovery behavior to predict a link's operating margins. This webinar shows how SerDes IP models and new simulation tools can be used to co-optimize a SerDes IP configuration and channel design, resulting in greatly improved productivity and profitability for your organization.This webinar focuses on the following topics:
How equalization compensates for loss in serial channels
Simulation requirements for serial links
IBIS-AMI: standardized, interoperable models for SerDes IP
Extending the life of existing systems with new SerDes IP
Serial link simulation and Bit-Error Rate (BER) prediction
Co-optimizing channel design and SerDes IP settings for optimum performance
Analyzing crosstalk and its impact on Bit-Error Rate
How to enhance your product’s performance while minimizing design cost and retaining compatibility
Designing with DDR3: Integrating Signal Integrity and Timing Analysis
DDR3 specifications call for operating speeds of 800-1600 MT/s with timing margins well under 100ps. Tight control of PCB layout is mandatory and detailed timing / SI analysis is required to ensure adequate design timing and voltage margins. DDR3 presents new high-speed design challenges since controllers can vary their output timing dynamically using a process known as "write leveling". This simplifies board-level routing but can complicate high-speed design analysis, since signal integrity and timing analysis must now be performed on a per-lane basis. Successful DDR3 design requires an integrated approach to system-level timing and signal integrity that models detailed signal behavior and reduces analysis integration error to a minimum. This requires a comprehensive understanding of component timing specifications and a corresponding set of simulation strategies. This complimentary webinar focuses on the following topics:
DDR3 module "fly-by" routing; implications for timing / SI analysis
New signal quality requirements for DDR3
SiSoft’s programmable DDR3 controller timing model
Integrated DDR3 timing/signal integrity flow
SiSoft Architectural/Validation Design Kits for DDR3 Design
Bowling for Picoseconds: Integrating DDR2/DDR3 Signal Integrity and Timing Analysis
DDR2 designs now operate at speeds of 800 MT/s, with timing margins in the sub-100ps range. At these speeds, tight control of PCB layout is mandatory and detailed timing / SI analysis is needed to ensure design margins are properly centered. DDR2 component timing specifications document the exact conditions under which device timing is measured and guaranteed. These specifications are complex, varying based on device pin class, operating speed, rising vs. falling edge and input slew rate. Determining interface margin to the sub-100ps level requires making detailed signal integrity interconnect delay measurements based on how component timing is specified. Those interconnect delay measurements must then be properly integrated into a timing model for the overall interface. This is simple in concept but difficult in actual practice. This complimentary webinar focuses on the following topics:
DDR2 component timing specifications and measurement conditions
Normalizing SI analyses to produce interconnect delays suitable for inclusion into interface timing models
Differences between DDR2 and DDR3 architectures; implications for timing / SI analysis
