Noise Model Verified On IQM’s Superconducting Quantum Chip
Noise Model Recent Research Highlights A Key Testbed for Quantum Computing Accuracy: the IQM 20-Qubit Chip
The fast emerging science of quantum computing has advanced by using IQM Quantum Computers' 20-qubit superconducting device to evaluate a new and extremely precise noise model. This study by IQM Quantum Computers, Ludwig-Maximilians-Universität München, and science + computing AG / Eviden's T. Piskor, M. Schöndorf, and M. Bauer greatly improves noise-related problems in the noisy intermediate-scale quantum (NISQ) era.
The new model, which has been rigorously benchmarked on the IQM device, promises to improve quantum processing and algorithm optimisation by authentically representing quantum hardware's complex behaviour.
Need for Noise Modelling in NISQ Era Quantum computing offers great potential for tackling problems that classical machines cannot, from optimisation to quantum simulation. However, all modern quantum computers are NISQ devices, which limits the number of error-prone operations before hardware noise degrades quantum characteristics. Understanding, reducing, and suppressing noise is crucial for quantum computer development. For identifying noise origins and assessing if a quantum algorithm works on a given hardware, detailed noise models that accurately reflect quantum devices are needed. IQMs 20-Qubit Chip: Verification Basis This unique noise model was verified on the IQM 20-qubit superconducting device. This gadget relies on square grid superconducting Transmon qubits. Its architecture relies on tunable couplers between each qubit to implement the chip's native entangling gate and reduce crosstalk. For single-qubit operations, the chip uses the PRX gate to rotate the Bloch sphere freely around the X-Y plane. PRX and CZ gates form a comprehensive gate set for IQM quantum computing hardware.
With this 20-qubit device, IQM has set high performance expectations for superconducting qubits, which must be understood. Tunable couplers have been shown to have fidelity above 99.8% at extended distances. Careful Noise Analysis Noise affects the IQM 20-qubit chip, like other quantum computing devices. This work meticulously determined the chip's noise parameters using coherence time measurements and randomised benchmarking sessions. Every qubit or qubit pair is measured for three critical criteria to ensure precision: Single-qubit gate timing and fidelity. At 20 ns, single-qubit gate integrity averaged 99.85%. Two-qubit gate timing and fidelity. Average two-qubit gate fidelity was 98.59% at 40 ns. Relaxation time describes qubit-environment energy transfer. 41.8 µs was the average time. Depolarisation time, which erases qubit phase information. The average time was 3.2 µs. Measurement error probability in states 0 and 1. At states 0 and 1, measurement error probabilities averaged 2.66% and 5.09%. These measurements fed the new noise model to build a “digital twin” of the IQM 20-qubit processor.
Benchmarking and Best Predictions More accurate predictions and benchmarking The model was validated on the IQM 20-qubit chip using a variety of benchmark circuits (structured and random) and sizes (2–7 qubits with depths 5–87). These included Quantum Approximate Optimisation Algorithm (QAOA), Random Unitary (RU), and Greenberger-Horne-Zeilinger (GHZ) circuits. Every circuit was carefully built to match the target hardware's native gate set and architecture, often requiring gate translation and SWAP insertion using Eviden's Qaptiva framework's Nnizer plugin.
For quantitative comparison, the Hellinger distance was used, which is ideal for comparing probability distributions from noisy quantum states since it accounts for events with noiseless zero-probability contributions. The benchmarking results demonstrated that the new noise model simulations and IQM chip experimental data agreed well. Hellinger distances were always below 0.1 for smaller circuits like GHZ-2 to GHZ-5, ensuring practically perfect agreement. Even for larger circuits like GHZ-6, GHZ-7, RU, and QAOA, the model accurately simulated hardware behaviour. Even at deeper depths, Hellinger distances for RU and QAOA circuits were below 0.1. The model accurately simulated the hardware outputs for QAOA circuits, which were practically random sampling due to their depth, to evaluate the results of very large and noisy circuits. Comparing the new method to other noise models, such as the unified noise model (UNM) and the Qiskit composite model (QiskitCM), which were previously studied on IBM Q Melbourne, showed its increased performance. The new model reduced Hellinger distances by over 50% for larger quantum walk circuits (QW-4, QW-5, and QW-6) tested on IBM Q Melbourne compared to competing models. The researchers attribute this large boost to their enhanced idle qubit noise modelling.
Future of Quantum Computing Potential for Quantum Computing The validation of this precise and adaptable noise model on the IQM 20-qubit chip is a major quantum computing development. By providing a more accurate representation of quantum hardware behaviour, it helps researchers evaluate and optimise quantum algorithms before implementing them on expensive and resource-constrained real quantum hardware. It also supports critical applications like error mitigation. The model agrees well, although the researchers notice slight deviations, likely due by more complex noise sources including coherence problems, leakage, and crosstalk that have not yet been completely represented. These advanced error channels will be used in future research to improve the model. The model should also be tested on neutral atom and trapped-ion quantum computer systems. This study is critical to understanding hardware limits and optimising algorithms for important and reliable outcomes in the noisy quantum age. The IQM 20-qubit chip's detailed characterisation and benchmarking help.