#series resistance

[drawittoknowitmedical]

VASCULAR RESISTANCE

The impediment to blood flow

Total peripheral resistance (aka, systemic vascular resistance)

Describes the resistance to blood flow throughout the entire systemic vasculature (throughout the entire body).

Vascular resistance

Resistance within a single organ; for example, resistance within in the kidney.

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Stability region of LDO stabilizator equivalent series resistance

This text studies LDO stabilizator equivalent series resistance (ESR) Stability region of the value. Discuss LDO frequency response by LDO stabilizator ac mode. Examine the steady and unstable ESR range. LDO stabilizator ac mode Fig. 1 shows the major component of PMOS LDO stabilizator. LDO stabilizator can be divided into 4 independent functional blocks: Through component, basic reference, take a sample resistor and error amplifier. The error amplifier is by bringing capacitor Cpar and transconductance ga simulation that the resistor Rpar supports. Depend on the parameter (Cpar, Rpar) for a living Show output impedence and series connection of the error amplifier pass the input impedance of the component. The series connection passes the component (PMOS transistor-resistor logic) Use the transconductance gp small signal mode simulation. Increase an output capacitor Co ' Equivalent series resistance RESR) And by-pass capacitor Cb. Can have output impedence from Fig. 1: Zo =R12P| ( RESR+1 / SCo) | 1 / SCo (1) =R12p(1+SRESRCo) /S2R12pRESRCb+S[(R12p+RESR) Co+R12pCb]+1 In the type R12p=Rds| (R1+R2) ≈ Rds (2) Usually, output capacitor value Co is far greater than the by-pass capacitor Cb far. So, output impedence Zo is similar to being expressed as: Zo≈ Rds (1+SRESRCo) /[1+S(Rds+RESR) Co]+[1+S(Rds | RESR) Cb] (3) From the equation ( 3) ,Receive a part of the total open-loop transfer function of the stabilizator, try to get zero and the limit. The first limit is: Po; S( Rds+RESR) Co =-1 (4) So fpo =-1 / 2π (Rds +RESR) Co≈ - 1 / 2π RdsCo (because R is greater than or equal to RESR) ( 5) Try to get the second limit from the equation 3: Pb; S(Rds | RESR) Cb =-1 (6) So fpb =-1 / 2π (Rds | RESRCb) ≈ - 1 / 2π RESRCb (7) The zero is: ZESR; SRESR Co =-1 (8) So fz (ESR) =-1 / 2π RESRCo (9) In addition, pass the component input impedance (namely amplifier output impedence Rpar, CPAR) Other limit exists. Limit and zero that LDO stabilizator is similar to are provided by the following formula: Po≈ 1 / 2π RdsCo≈ IL / 2π VACo (10) Pb≈ 1 / 2π RESRCb (11) Pa≈ 1 / 2π RparCpar (12) ZESR≈ 1 / 2π RESRCo (13) In the type: RDs≈ VA / IL, VA =1 / λ (MOS device) ,λ is that the channel length modulates the parameter. The limit Pa is being only adopted through the input of the device, the output in the device is not being used. According to limit and zero obtained, get the typical frequency response of LDO stabilizator, see Fig. 2. The limit Po depends on the load current. As the low load current, the limit is responded to and taken place in quite low frequency, so, reduce the phase margin. The worst stability appears in ESR limiting value and low load current. ESR stability region LDO stabilizator need one output capacitor ' Export the equivalent series resistor) To control the cycle steadily. ,If does not compensate, LDO has two pieces of limit which cause the unstability. Obviously, the linear voltage regulator is not stable, this is because in a gain frequency (UGF) Phase shift spend for 180 ' Namely phase margin =0 degrees) ,This is because of in two pieces of limit (Po, Pa) of low frequency Due to influence. In order to stablize stabilizator, must increase the zero, it is influenced that the zero will dispel the phase place one of two pieces of limit. Output capacitor ESR or compensating the series resistor (CSR) Used in the zero. Fig. 4 shows ESR ' Or CSR) How the zero controls the cycle steadily. The zero produced by ESR is positioned before UGF, the phase margin in UGF1 will be greater than 0 degrees like this. So, the linear voltage regulator becomes steady. For the stability of the system, control the phase margin of the cycle in UGF should be greater than 0 degrees. ESR value should keep determining the stable range of cycle. In most cases, the intersection of LDO and minimum stabilizator / maximum ESR value. We can see from equation 11 and 13, ESR determines zero Zesr and the limit Pb. When ESR changes, Zesr and Pb are up/down to drift about, influences cycle stability. LDO not stable frequency response, LDO not stable frequency response while showing ESR too small of Fig. 6 while showing ESR too big of Fig. 5. The phase margin in UGF is less than or equal to 0 degrees, cause the system to be unstable under these two kinds of situations. Fig. 5 and Fig. 6 show the stability region of Zers. Because ESR can cause the unstability, LDO manufacturers generally offer and represent the diagram of stability regions of ESR value. Fig. 7 shows the typical range (TPS76933 3.3V LDO stabilizator) of ESR value relative to output current . This curve is called the death tunnel (Tunnel of Death) . It must be between 0.1Ω and 8Ω that this curve shows ESR. Tantalum is electrolyzed, aluminium is electrolyzed and the multi-layer ceramic capacitor can meet ESR requirement. Source: With Africa net