Jun 12, 2019
This blog presents SoC- (System on Chip) level functional verification flow. It also describes ways to speed up the process. To ensure successful tapeout of SoCs, here are the steps of a standard SoC-level Functional Verification flow.
1. SoC Level/Top Level view (Feature Extractions) During SoC verification, you must view the design at the top level and extract its SoC level functionality/features during specification study phase for its verification. At this stage, a thorough understanding of SoC functionality and its architecture is required because misunderstanding of the specification can become the leading
