Interview Questions Related to VLSI
Interview Questions Related to VLSI.
In which field are you interested?
Can you talk about low power techniques?
How low power and latest 90nm/65nm technologies are related?
Do you know about input vector controlled method of leakage reduction?
How can you reduce dynamic power? What are the vectors of dynamic power? How will you Computes a target IR drop value in the core from the target IR drop value.
How will you do power planning? How to estimate the static power? How to estimate the dynamic power?
Interview Questions Related to VLSI.
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How EM & IR taken into account during power planning.If you have both IR drop and congestion how will you fix it? Is increasing power line width and providing more number of straps are the only solution to IR drop? In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why? In which case we insert buffer to fix setup? How will you decide best floorplan? What is the most challenging job in P&R flow? How will you synthesize clock tree? How many clocks were there in this project? How did you handle all those clocks? Are they come from seperate external resources or PLL? Why buffers are used in clock tree?
What is cross talk? How can you avoid cross talk? How shielding avoids crosstalk problem? What exactly happens there? How spacing helps in reducing crosstalk noise?
Why double spacing and multiple vias are used related to clock? How buffer can be used in victim to avoid crosstalk?
What parameters (or aspects) differentiate Chip Design and Block level design? How do you place macros in a full chip design?
Differentiate between a Hierarchical Design and flat design?
Which is more complicated when u have a 48 MHz and 500 MHz clock design?
Name few tools which you used for physical verification? If the routing congestion exists between two macros, then what will you do? How will you decide the die size?
Interview Questions Related to VLSI