VHDL Lesson #1 Code structure
I am starting off the series with the second chapter of the book since the first chapter is more of a history lesson and if you are following this segment you likely somewhat understand what VHDL is and FPGAs are. In short chapter one goes over when and why VHDL was invented as well as a couple of examples.
I have started a repository on GITHUB for any Example code I come up with. GITHUB is like a programmer's social website where you can post code publicly and people can comment on it as well as offer improvements. It is also a great place to ask for help if you have a bug in the code you happen to be working with.
VHDL is an IEEE standard and for that matter is very structured. The Basic code structure looks something like this.
This one is pretty self explanatory if you have coded in most any language. Here you import the libraries that you need for the functions that you will use in your project. It is important to realize that these libraries actually contain subsections that can also be called out so that you do not have to import the whole library. Inside each library there are a set of packages that contain Functions, Procedures, Components and Types. A typical declaration looks like this:
USE library_name.package_name.package_parts;
This is where you set up what each pin does. Programmable logic devices such as FPGAs are able to configure their pins as inputs or outputs. The entity tells the device what pins are being used and how they are being used. A typical Entity entery looks something like this:
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
Here is where you are able to tell the circuit how you would like it yo behave. Each entity can be manipulated here and molded to your exact specifications. A typical architecture entry looks like this:
ARCHITECTURE architecture_name OF entity_name IS
Piecing together the examples above we end up with a VHDL file that looks like this:
-------------------------------------------------------------------
-- VHDL code structure example code
-- EEUnited.tumblr.com
--
-- This file is an example of the structures inside of a VHDL
-- Code Example Based on examples from the first chapter of
-- "Circuit Design with VHDL" by Volnei A. Pedroni
--
-------------------------------------------------------------------
-- Library Declarations
-------------------------------------------------------------------
LIBRARY library_name; --Comment
USE library_name.package_name.package_parts; --comment
-- Entity
-------------------------------------------------------------------
ENTITY entity_name IS
PORT (
Port_name : signal_mode signal_type;
Port_name : signal_mode signal_type;
...)
END entity_name;
-- Architecture
-------------------------------------------------------------------
ARCHITECTURE architecture_name OF entity_name IS
[declarations]
BEGIN
(code)
END architecture_name;
At the end of the chapter there are actual code examples for D-Flip-Flops, AND gates, Or Gates, and a few other relatively simple circuits.
Next chapter is about data types. Till then Blog you later.
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