#cadv

[b-uchanans]

#sleepy babies

[b-uchanans]

we’re slowly falling through the night 

cloak & dagger 1x01: first light

[b-uchanans]

#why do i find this so cute i even made gifs ouf of it

bonus:

[yss120993-blog]

CADV- COMPUTER AIDED DESIGN FOR VLSI

I Complexity in microelectronic circuit design and Moore’s Law, design styles -Fullcustom design, standard-cell design, Programmable Logic Devices, Field Programmable Gate Arrays, Design Stages, Computer-Aided Synthesis and Optimizations, design flow and related problems.

II Boolean functions and its representations – co-factor, unite, derivatives, consensus and smoothing; tabular representations and Binary Decision Diagram (BDD), OBDD, ROBDD and Bryant’s reduction algorithm and ITE algorithm. Hardware abstract models – structures and logic networks, State diagram, data-flow and sequencing graphs, hierarchical sequencing graphs. Compilation and behavioral optimizations.

III Architectural Synthesis – Circuit description and problem definition, temporal and spatial domain scheduling, synchronization problem. Scheduling algorithms - ASAP and ALAP scheduling algorithms, scheduling under constraints, relative scheduling, list scheduling heuristic. Scheduling in pipelined circuits.

IV Resource Sharing & Binding in sequencing graphs for resource dominated circuits, sharing of registers and busses; binding variables to registers. Two-level logic optimization principles – definitions and exact logic minimizations. Positional cube notations, functions with multi-valued logic. List-oriented manipulations.

V Physical Design. Floor planning – goals and objectives. Channel definition, I/O and power planning. Clock Planning. Placement – goals and objectives. Placement algorithms. Iterative improvement algorithms. Simulated Annealing. Timing-driven Placement. Global routing – goals and objectives. Global routing methods. Timingdriven global routing. Detailed Routing – goals and objectives. Left-edge algorithm. Constraints and routing graphs. Channel routing algorithms. Via minimization. Clock routing, power routing, circuit extraction and Design Rule Checking.