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[yss120993-blog]

[yss120993-blog]

INTRODUCTION TO VLSI

I

Introduction to MOS Technology: Basic MOS transistors, Enhancement Mode transistor action, Depletion Mode transistor action, NMOS and CMOS fabrication.

II

Basic Electrical Properties of MOS Circuits:I versus Vrelationship, Aspects of threshold voltage, Transistor Trans conductance gm. The NMOS inverter, Pull up to Pull-down ratio for a NMOS Inverter and CMOS Inverter(B/B ), MOS transistor circuit Model, Noise Margin.

III

CMOS Logic Circuits:The inverter, Combinational Logic, NAND Gate NOR gate, Compound Gates, 2 input CMOS Multiplexer, Memory latches and registers Transmission Gate, Gate delays, CMOS-Gate Transistor sizing, Power dissipation

IV

Basic Physical Design of Simple Gates and Layout Issues: Layout issues for inverter, Layout for NAND and NOR Gates, Complex Logic gates Layout, Layout optimization for performance.

V

Introduction to VHDL, Verilog & other design tools. VHDL Code for simple Logic gates, flip-flops, shift-registers, Counters, Multiplexers, adders and subtractors

[yss120993-blog]

CADV- COMPUTER AIDED DESIGN FOR VLSI

I Complexity in microelectronic circuit design and Moore’s Law, design styles -Fullcustom design, standard-cell design, Programmable Logic Devices, Field Programmable Gate Arrays, Design Stages, Computer-Aided Synthesis and Optimizations, design flow and related problems.

II Boolean functions and its representations – co-factor, unite, derivatives, consensus and smoothing; tabular representations and Binary Decision Diagram (BDD), OBDD, ROBDD and Bryant’s reduction algorithm and ITE algorithm. Hardware abstract models – structures and logic networks, State diagram, data-flow and sequencing graphs, hierarchical sequencing graphs. Compilation and behavioral optimizations.

III Architectural Synthesis – Circuit description and problem definition, temporal and spatial domain scheduling, synchronization problem. Scheduling algorithms - ASAP and ALAP scheduling algorithms, scheduling under constraints, relative scheduling, list scheduling heuristic. Scheduling in pipelined circuits.

IV Resource Sharing & Binding in sequencing graphs for resource dominated circuits, sharing of registers and busses; binding variables to registers. Two-level logic optimization principles – definitions and exact logic minimizations. Positional cube notations, functions with multi-valued logic. List-oriented manipulations.

V Physical Design. Floor planning – goals and objectives. Channel definition, I/O and power planning. Clock Planning. Placement – goals and objectives. Placement algorithms. Iterative improvement algorithms. Simulated Annealing. Timing-driven Placement. Global routing – goals and objectives. Global routing methods. Timingdriven global routing. Detailed Routing – goals and objectives. Left-edge algorithm. Constraints and routing graphs. Channel routing algorithms. Via minimization. Clock routing, power routing, circuit extraction and Design Rule Checking.