Zarlink introduces the strong chip to make up: Solve from enterprise to all applied circuit card clocks of the core
Uniting the semi-conductive company eminently introduces the chip association of a pair of clocks today, it is SONET/SDH (synchronous fiber optic net / synchronous digital hierarchy) And PDH (Plesiochronous Digital Hierarchy) The system offers the industry most complete function collecting and optimum performance. Zhuo Lian's DPLL (figure PLL) And APLL (simulation PLL) To the card application of circuit from enterprise to central extensive field of the network. With complicated network framework and arrangement for the higher speed transfer system day by day, reliable network clock and synchronous acquisition become more and more difficult. In order to guarantee one grade of characteristics of telecommunication, the apparatus must be used and made up before and after DPLL and APLL and offered superior clock function and characteristic, respond to the request that the system is compatible with the greater shaky redundancy at the same time. However, the scheme on the market needs a plurality of products of different producers of simultaneously using at present, make, shake characteristic and function collect unable to up to optimizing often. These two new chips of Zhuo Lian's are directed against the settlement of the above-mentioned basic problem directly. Compared with competition products, ZL 30106 DPLL redundancy of having incomparable OC-3 to shake, have offered the industry most complete function association including that the seamless consults and switches over, consults and monitors and keeps. Combine ZL30416 APLL, Zhuo Lian's DPLL frequency synthesis technology with the independent property right can minimize the phase noise of low frequency, thus characteristic and errorless transmission of allowing the designer and optimizing APLL bandwidth and obtaining whole the superior one to shake. " Zhuo Lian offers the a full range of digital sum simulation clock products for broadband network system of high-speed growth, such as gateway, DSLAM, insertion and separation multiplexer of metropolitan area, router and high-speed apparatus of final mile,etc., " Unite semi-conductive company clock and synchronous marketing manager Darren Ladouceur of product division and say eminently. " Combine our clock card PLL, the highest canonial clock function on all circuit card product exhibition markets of ours and shaking to manage the characteristic. We realize one grade of clock systems of telecommunication is offered the clock solution of single producer, unique individual character for the customer, shorten listing time and reduce the cost. " The best to shake and take shape It means the clock in the clock system is exported and managed and filtered to shake and take shape. General DPLL will produce the wideband phase noise of all frequency, makes so that APLL filter it more difficult, therefore has reduced the characteristic of shaking wholly. Zhuo Lian's frequency DPLL comprehensive technology can filtrate the phase noise of low frequency effectively, therefore the designer can be absorbed in APLL dispelling this key function of the high-frequency phase noise. Zhuo Lian has already proved this device can obtain whole optimal low frequency characteristic and superior one and shake to make the characteristic up. DPLL of the full-function ZL30106 DPLL can realize the synchronism of SONET/SDH and PDH circuit card. Except have 20 psRMS (psec, root mean square) Industry lead to shake outside characteristic,lie in yet, it can consult mainly inputting and auxiliary input is consulted on the clock - synchronous pulse pair synchronously. Device this can accept three input consult, offer, export the clock while being a series of, can get 0.01 Ppm (a million proportion by subtraction) Maintenance frequency accuracy. ZL30106 DPLL offers the manual or automatic seamless to consult and switch over choosing. Accord with canonial and a lot of and plant APLL ZL30416 APLL, in order that SONET/SDH apparatus shakes to decay and the speed is changed, specially in order to meet it from designing on OC-3/STM-1 to circuit card applied function and performance requirement of OC-192/STM-64 transmission rate. Chip this can produce satisfied to have, shake to Telcordia GR-253-CORE that include OC-192 standard norm very much low to shake to export the clock, accord with, have, select items of 1 and select item 2 shake, produce requirement to G.813 that include STM-64 standard at the same time. Price and supplying the situation ZL30106 and ZL30416 chip already been produced in batches now. ZL30106 DPLL adopts 64 guide (slim flat pack all sides), TQFP of foot, Capsulate, the unit price at the time of a thousand scenes of batch is 15.00 dollars. ZL30416 APLL adopts 64 guides the foot CABGA (the ball grid array of chip) Capsulate, the unit price at the time of a thousand scenes of batch is 36.19 dollars. It please visit to understand more information: http://products.Zarlink.com/product_profiles/ZL30106 And http://products.zarlink.com/product_profiles/ZL30416. www.zarlink.com