Dezhou instrument introduces the most high-performance high integration density clock multiplier of industry
A few days ago, Dezhou instrument introduced the phase locking ring (PLL) on having three The high integration density regular IC of the assembly of the electric-wave filter, it has optimal characteristic of the industry at present. The framework of this new clock multiplier does not need to connect the assembly to support PLL structure, thus not only has reduced the overall system cost, but also saved the board-level space notably. Because cycle shakes extremely low, and have ability to produce much clock rate, so support this device technology to be very suitable for game system, DVD broadcaster / consumption electronic products such as CD writer, digital television and set-box,etc.. (If want to understand more information, please visit www.ti.com/sc04169. ) Through 54 MHz system clock, CDC5806 can be produced video, audio frequency, CPU, USB and walkie memory clock by the single device. Three PLLs can produce various output frequency from the system clock. Loop filter and internal antireaction adopt the necessity of the external assembly on slice. CDC5806 adopts RF Si-Ge craft of TI to develop, have realized the clock is assigned and low the extremely low peak shake by peak cycle to shake and low to 150 psec. It contributes to reducing electromagnetic disturbance to adopt the future clock that this craft develops and integrate (EMI) Function,such as variable spread spectrum definite time (SSC) When. Variable SSC still enables designer to carry on the fine setting to its design, carries on the test of various standard SSC in the system. TI technology still keeps the excellent PLL frequency isolating while realizing these functions and integrating. CDC5806 has the following key characteristics: " Allow the clock input of the single end LVCMOS; " Use the generable much output frequency of systematic clock input of 54.000 MHz; " It is assigned and low to be used in the clock and shake; " Working voltage is 3.3V form power; " The following generable clock: OVIDCLK 74.175824 MHz/54 MHz (tape is buffered) ; oAUDCLK 16.9344 MHz/12.288 MHz; oCPUCLK 64 MHz; oUSBCLK 48 MHz; oSPCLK 32 MHz; oMSCLK 38.4 MHz/19.2 MHz/12 MHz; " Integrate PLL electric-wave filter assembly; " The characteristic that the extremely low peak shakes by peak cycle, it is 150 psec to be the lowest; " The temperature range of industry is lain between - between 85 C; Stock situation CDC5806 adopts 20 to guide the foot TSSOP to capsulate, has already begun to supply, can authorize the retail trader to order through TI and at present. When the batch is a thousand sets, the suggested retail price is 2.15 dollars. www.ti.com/clocks