#high-level synthesis

[reportwire]

Silexica Joins Xilinx Developer Forum 2019 as a Diamond Sponsor

Silexica Joins Xilinx Developer Forum 2019 as a Diamond Sponsor

Silexica will demonstrate SLX FPGA working together with Xilinx Vivado High-Level Synthesis Press Release – updated: Sep 16, 2019 SAN JOSE, Calif., September 16, 2019 (Newswire.com) – Silexica (silexica.com) announced today that they are joining the Xilinx Developer Forum (XDF) 2019 as a Diamond Sponsor at three forums: XDF Americas in Silicon Valley (US), XDF Europe in The Hague (NL) and XDF…

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[reportwire]

SLX FPGA v2019.4 Delivers an Average of 45x HLS Performance Improvement

SLX FPGA v2019.4 Delivers an Average of 45x HLS Performance Improvement

Press Release – updated: Dec 16, 2019 SAN JOSE, Calif., December 16, 2019 (Newswire.com) – Silexica (silexica.com) has announced the release of SLX FPGA v19.4, designed to help developers prepare and optimize C/C++ code for high-level synthesis (HLS) in Xilinx’s VivadoTM and VitisTM HLS design flows. SLX FPGA v19.4 provides performance improvements that deliver, on average, a 45x increase in…

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