#memory hierarchy

[arinewman7]

Memory Hierarchy

Rebecca Orcutt

oil on canvas

[peachmelbaesunpostre]

[ijtsrd]

A Performance Degradation Tolerance Way Tagged Cache 

by Karkagari Anjali | G. Kumara Swamy | M. Preethi" A Performance Degradation Tolerance Way Tagged Cache" 

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-5 , August 2018, 

URL: http://www.ijtsrd.com/papers/ijtsrd15729.pdf 

Direct URL: http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/15729/a-performance-degradation-tolerance-way-tagged-cache/karkagari-anjali

international journals in engineering, engineering journal, paper publication for engineering

For an electronic product or chip if functional faults exist, then the product or chip is of no use. Therefore, if we take a cache memory, a secondary memory for high-speed retrieval of data stored where functional faults exist. These functional faults in the data stored in the cache can be converted into performance faults so that the caches can still be marketable. In processors, caches are designed as Level 1(L1), Level 2(L2), and the least hard disk. If the processor wants the data fromto memory it checks the availability of data in upper-level cache L1 and if the data is found it sends to the processor. If the data is not found in L1, it checks in lower level cache L2 and next in L3 and at the least in slow memory or hard disk. So, in this process, many functional faults may exist which leads to making the processor faulty. So, to protect the cache memory ECC and BIST are used. For a cache redesign, a PDT cache is used where functional faults are converted into performance faults. We propose a new PDT way tagged cache design which leads to increased performance. This reduces fault rate with small hardware overhead by applying BIST or ECC method. 

[woodvavb027-blog]

The Fractal Structure of Data Reference:: Applications to the Memory Hierarchy (Advances in Database Systems)

The Fractal Structure of Data Reference:: Applications to the Memory Hierarchy (Advances in Database Systems) The architectural concept of a memory hierarchy has been immensely successful, making possible today's spectacular pace of technology evolution in both the volume of data and the speed of data access. Its success is difficult to understand, however, when examined within the traditional "memoryless" framework of performance analysis. The `memoryless' framework cannot properly reflect a memory hierarchy's ability to take advantage of patterns of data use that are transient. The Fractal Structure of Data Reference: Applications to the Memory Hierarchy both introduces, and justifies empirically, an alternative modeling framework in which arrivals are driven by a statistically self-similar underlying process, and are transient in nature. The substance of this book comes from the ability of the model to impose a mathematically tractable structure on important problems involving the operation and performance of a memory hierarchy. It describes events as they play out at a wide range of time scales, from the operation of file buffers and storage control cache, to a statistical view of entire disk storage applications. Striking insights are obtained about how memory hierarchies work, and how to exploit them to best advantage. The emphasis is on the practical application of such results. The Fractal Structure of Data Reference: Applications to the Memory Hierarchy will be of interest to professionals working in the area of applied computer performance and capacity planning, particularly those with a focus on disk storage. The book is also an excellent reference for those interested in database and data structure research. Thе Frасtаl Strǖсtµrе of Datа Rёfеrеnce:: Applíсαtìοns to thё Mеm0ry H¡еrarсhy (Advаncеs ¡n Datαвasе SУstems)