How is the parasitic capacitance of a MOSFET formed?
The core of power semiconductors is the PN junction. From diodes and transistors to field-effect transistors, all are applications based on the characteristics of the PN junction. Field-effect transistors are categorized into junction-type and insulated-gate-type, with the insulated-gate-type also known as MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors).
Based on whether an inversion layer exists in the off state, MOSFETs can be classified into enhancement-mode and depletion-mode types.
Causes of Parasitic Capacitance Formation
1. Barrier Capacitance: In power semiconductors, when N-type and P-type semiconductors are joined, concentration differences cause electrons from the N-type semiconductor to partially diffuse into the holes of the P-type semiconductor. Consequently, space charge regions form on both sides of the junction interface (the electric field generated by this space charge region impedes diffusion movement, ultimately leading to diffusion equilibrium). ;
Diffusion Capacitance: When a forward voltage is applied, the concentration of non-equilibrium minority carriers is high near the depletion layer boundary and low farther away, gradually decreasing to zero. As the applied forward voltage increases, both the concentration of non-equilibrium minority carriers and the concentration gradient increase; when the applied voltage decreases, the opposite occurs. This phenomenon involves charge accumulation and release processes identical to capacitor charging and discharging, termed diffusion capacitance.
The parasitic capacitance structure of a MOSFET is as follows, where factors such as polysilicon width, channel and trench widths, gate oxide thickness, and PN junction doping profiles all influence parasitic capacitance.
Regarding the definitions of the three capacitance parameters in MOSFET datasheets:
Input capacitance Ciss = Cgs + Cgd;
Output capacitance Coss = Cds + Cgd;
Reverse transfer capacitance Crss = Cgd
These three capacitances are largely unaffected by temperature variations. Consequently, drive voltage and switching frequency significantly influence the switching characteristics of MOSFETs, while temperature effects are relatively minor.
II. Theoretical Derivation
Direct measurement of the gate-source capacitance using an LCR meter yields a value that represents the series and parallel combination of parasitic capacitances between the MOSFET's pins. Similarly, direct measurements of the capacitance between drain and gate, and between drain and source, also represent the combined effect of parasitic capacitances in series and parallel. So, based on these direct measurements, how can we calculate the distributed capacitance?
Below, we initially solve for the three parasitic capacitances based on these three equations. From the first equation, we obtain an expression for Cgs. Substituting this into the following two equations, we eliminate Cgs, leaving the other two capacitances to be solved for. The numerators on the right-hand side of these two equations are identical, thus allowing us to derive a new equation. At this point, manual derivation becomes somewhat complex. We lack confidence in continuing the solution manually. Solving these three nonlinear simultaneous equations is indeed challenging. We will now utilize software assistance for the solution.
III. Iterative Algorithm
Given the difficulty of direct calculation, we design an iterative algorithm. Based on the preceding formula, we derive an iterative equation for distributed capacitance. Initially, set the distributed capacitance to the measured capacitance value. Then, using the iterative formula, we obtain the updated value. This process continues iteratively until convergence is achieved, yielding the final solution. Given the origin of the iterative formula, it is readily apparent that the original distributed capacitance should be a stable point in this iterative process. However, whether this iterative process converges cannot be directly concluded at this stage.
Below, we simulate this iterative process using Python programming. Setting the three capacitors to 8000, 300, and 2000 pF respectively, we first calculate the three measured capacitance values. Next, use these three measured capacitances as the initial values for the distributed capacitance. Iteratively update the values below and plot the curve of iterations versus error. We can observe that the error decreases rapidly, approaching zero after approximately 20 iterations. This validates the correctness of the iterative algorithm.
IV. Actual Values
Using LCR tweezers, measure the capacitance between the three pins of the MOSFET. The measurement frequency is 10kHz, and the measurement voltage is 0.6V. However, the results indicate that these three values appear somewhat unusual. This primarily concerns the capacitance between the gate and drain, and between the drain and source. Both capacitances were significantly larger than the values specified in the chip's datasheet. The exact reason for this discrepancy remains unclear. Using the iterative algorithm from earlier to calculate the values of the three distributed capacitances revealed an issue: the capacitance between the gate and source was negative. This further indicated that the previously measured capacitance values were unreasonable.
By adjusting the measurement signal amplitude in the LCR meter to 0.3V, the measured values changed. Using the new measurement mechanism and the iterative formula, the parasitic capacitances within the three MOSFET terminals were calculated. The calculated results were all positive values. However, their magnitudes still differed from the ranges specified in the actual MOSFET datasheet. This discrepancy stemmed from the LCR meter's inaccurate measurement of the capacitance values across the three pins. This measurement error likely resulted from the MOSFET not being properly voltage-biased.
