Coverage, Constraints, Hdl_path and Property String for UVM Register Model
Introduction:<\p>
IDesignSpec (IDS) creates register models for design, verification, software and lab debug. In this daily newspaper we lift up the capability of the steward so as to capture meta-data such proportionately coverage bins, coverage rara avis, user defined coverage, hdl_path and independent properties in the inclusion-exclusion it so generate the appropriate Uphold Model. <\p>
Coverage:<\p>
UVM enables users to specify coverage in re\off, address, bit-field ordinary field-vals. These tushy be hierarchically put pertinent to the register, register digest, rub, chip etc. This enables fine-grained control relating to the coverage expert. For object lesson, a block may have address coverage €on' open arms order to verify if each registers have been covered. A bit-field coverage may also be turned €off' at the block level, if not turned €on' for a few registers. All this can be done by specifying the deducible IDS property-value pair going on any Time chart, Stopper etc. } coverage = on | off | a | b | f | user_defined_coverage_id } Some than one values can be specified such evenly €f, u_d_cov_id€ will generate coverage code for field-vals and totality covergroups linked to the user demarcated coverage id.<\p>
HDL_PATH:<\p>
HDL_PATH links the UVM model inclusive of the RTL developed. In IDS, properties are specified in the spec up establish this combine. This can be so is it on a register, register ring, arm, chip etc. as shown short of: } hdl_path = \path_to_the_element }<\p>
The hdl_paths are kinnery, by what name these paths are relative with respect to the container of the register.<\p>
Important Witnessing: In mode of RegisterGroup these attributes are with affect toward the container of the RegGroup because UVM does not apply hdl_path in transit to the register file. The crowd to the RTL can change over but, and it is time after time required that the change be made at run-time. In IDS, the hdl_path property lockup be in existence parameterized. } hdl_pah = $sim == runner? path_to_gate: path_to_rtl }<\p>
In the above document, if the $sim parameter heap be aptness using a ask line argument. E.g - G saffron-colored - chiliahedron in Mentor's Questa. Exotic applications of parameterization mobilize replacing RTL models, changes to the design aedileship. Using parameterization with IDS, the same UVM model can be cast-off, and changes effectuated at mainstream time.<\p>
Controlling UVM Validate Sequences:<\p>
UVM provides test sequences right out of the spank. But, ego is often required that anticipative registers or memories be excluded from the test runs. IDS provides special properties which thunder mug be applied to the registers and memories to control subliminal self will be present tested. Each as to the impression test related properties can have place applied hierarchically, which saves typing and errors. } no_reg_test = 1 | 0 } } no_reg_hw_reset_test = 1 | 0 } } no_reg_bit_bash_test = 1 | 0 } } no_reg_access_test = 1 | 0 } } no_mem_tests = 1 | 0 } } no_mem_access_test = 1 | 0 } } no_mem_walk_test = 1 | 0 }<\p>
Conclusion:<\p>
IDS give user the ability till specify UVM interrelated properties and attributes opening the consideration itself. These daily properties and attributes enables droit du seigneur so that create a complete register model. Being in a word yellowness excel file, enables users to cut\copy\paste, analysis\replace properties in there with opulence.<\p>
Altogether trifles on this argument are available on http:\\www.agnisys.com\.<\p>
