Coverage, Constraints, Hdl_path and Property Escalator clause for UVM Register Model
Introduction:<\p>
IDesignSpec (IDS) creates bookkeeper models for design, verification, software and lab debug. In this paper we introduce the capability in connection with the spear to netting meta-data corresponding as coverage bins, coverage sort, user defined coverage, hdl_path and other properties in the specification itself in order to generate the correct Inscribe Model. <\p>
Coverage:<\p>
UVM enables users en route to specify coverage on\minus, address, bit-field or field-vals. These can be extant hierarchically put on the register, register group, block, chip etc. This enables fine-grained control on the coverage model. For example, a block may have praxis coverage €on' in order unto verify if all registers keep been covered. A bit-field coverage may also be turned €off' at the block level, all the same turned €on' insomuch as a few registers. All this box up be complete by specifying the following IDS property-value pair on any Register, Block etc. } coverage = on | disharmonic | a | b | f | user_defined_coverage_id } Inter alia omitting worldling values can be specified congenator as €f, u_d_cov_id€ will generate coverage code for field-vals and all covergroups allied to the user defined coverage id.<\p>
HDL_PATH:<\p>
HDL_PATH links the UVM miniature at any cost the RTL transcendent nonempirical concept. In IDS, properties are specified an in the spec toward establish this link. This be up to obtain done on a register, represent group, one small difficulty, incision etc. as shown below: } hdl_path = \path_to_the_element }<\p>
The hdl_paths are relative, so these paths are relative with respect to the container in regard to the great scale.<\p>
Important Interest: In case in relation to RegisterGroup these attributes are with respect to the container of the RegGroup because UVM does not apply hdl_path to the register arrange. The link headed for the RTL capsule equivocate over time, and number one is often imposed that the change be made at run-time. In IDS, the hdl_path quirk can be parameterized. } hdl_pah = $sim == gate? path_to_gate: path_to_rtl }<\p>
In the excelling example, if the $sim parameter can be set using a command line argument. E.fiver - G or - g in Mentor's Questa. Other applications in point of parameterization include replacing RTL models, changes in consideration of the design hierarchy. Using parameterization in IDS, the same UVM model can obtain acquainted with, and changes made at run time.<\p>
Prime UVM Fight Sequences:<\p>
UVM provides probatory sequences right out of the camp. However, it is often required that certain registers primrose memories be excluded from the test runs. IDS provides funicular properties which can be applied into the registers and memories to acme top brass will breathe tested. Each of the prosecution test of common source properties can be applied hierarchically, which saves typing and errors. } no_reg_test = 1 | 0 } } no_reg_hw_reset_test = 1 | 0 } } no_reg_bit_bash_test = 1 | 0 } } no_reg_access_test = 1 | 0 } } no_mem_tests = 1 | 0 } } no_mem_access_test = 1 | 0 } } no_mem_walk_test = 1 | 0 }<\p>
Sequelant:<\p>
IDS give user the ability to specify UVM related properties and attributes in the specification itself. These special properties and attributes enables user to create a complete register commendable. Extant entree a word or excel file, enables users to cut\copy\paste, search\replace properties with ease.<\p>
Make for details on this topic are available on http:\\www.agnisys.com\.<\p>
