10 great factors that DSP and data converter collaborative work must consider
Suppose you receive a task, designing one set is imitated the constituent signal processing system of the device by DSP, DAC and ADC,etc.. If you consider several important factors, it will be very simple to work. Next let us talk about these factors that should be considered in the design work.
It needs to understand and employing the type to understand and employ the type the first step in detail. As to the application of controlled, have already needed being to a large number of sporadic data processing situations, also consider the intermittent idle state; But to the application of audio frequency, need to deal with the ability of the serial data flow. Understand applied concrete demand will contribute to choosing appropriate interface and accurate data to read the method.
Assess systematic the intersection of speed and two-step, need, find out about speed of data sampling. For example, the voice system may be a CD broadcaster, the sampling rate is 96 kHz, and may be the audio system of the telephone too, the sampling rate is only 8 kHz. Certainly, it may be other systems too, such as ADSL mass measurement application, the sampling rate reaches 10 MSPS high, or weigh application, enough if sample 16 times per second, but require the definition with great (such as 24) . Understand the information in this respect, will contribute to launching the next work, namely choose the correct DSP interface.
Choose correct DSP interface understand, employ and after speed require, to adopt how many the intersection of DSP and interfaces there is certain understanding. Most audiofrequency apparatuses use the particular typological serial interface, but high-speed application requires the parallel interface. When the sampling rate is that 10 MSPS, resolution ratio are 12, if adopt the serial interface, it should reach 120 MHz ability to carry oral speed from converter to DSP transmission data. This requirement has exceeded most 50 MHz to carry oral handling capacity serially greatly. If use the parallel interface, then the frequency of handshake is 10 MHz on the bus line, the speed is reduced notably, so it is very simple to deal with. While choosing the interface, another question that considers is if also want, whether the parallel bus could meet the required data rate requirement, whether the chip of the parallel bus has already reached full load after meeting procedure and coefficient requirement in other words. If it is true, would there is no harm in considering that would insert FIFO between DSP and converter.
Confirmed that shook hands the mode once chooses DSP interface, will consider the hand-shake mode (handshake mode) between converter and DSP soon nexted . Most converters will all provide the end of conversion of a certain type before sending out the new data word (EOC) Signal. There are two kinds of ways in which the processor uses the above-mentioned signal: First, roll polling (poll) ; Second, use it as and cut off. Use EOC signal as and stop having the advantage of suring, because CPU will not be taken up by the roll polling mark, so will not interrupt the normal operation of CPU before getting the data. However, if the converter waits to deal with the particular agreement to read data fetch, for example converter send out end of conversion need, read order, come on retrieval data again behind the signal, each one will touch off new break to read the order, will cause too many expenses then, lose more than gain. In this case, the roll polling method has obvious advantages. If cut off very important of time delay, use the polling mode to have advantages even more. Roll polling can guarantee signal speed of response fast, is more fast than to enter routine of interrupt servicing this. If there are transient time slots in data retrieval (narrow timeslot) ,It is favorable too to adopt the polling mode.
Confirm the mode of transmission is to collect the machine format work actually next. There are two kinds of methods in data gathering, has his strong points. The first kind of method is DMA (direct memory access) which adopt DSP Control device, can make transmit and is in pace with conversion end mark of the converter, and make CPU undertake to transmit the work, because the packing of data array is finished in the backstage, transmit and finish, notify CPU. However, this kind of method is only valid on condition that carry on direct transmission. If the data converter needs some complicated mechanisms in the retrieval data, then DMA is not very effective. In this case, should let CPU participate in transmitting the work. Obey special agreement to be quite simple, must use a large number of the intersection of CPU and resource come on data gathering. If the interrupt rate is very high, then CPU may be very difficult to go to carry out the algorithm after data collection again if having time.
Whether adopt the data to burst and suppose the parallel bus that the data converter connected to DSP, this parallel bus is in memory access (read the data carrying out) And I/O deposits and withdraws (read and sample) Between need several piece not to be periodic by conversion,and whether it is getting higher very in conversion rate in data, so, it is often essential to change, nearly sample and read needing to change each time. If one step can read a plurality of data words, and does not need to all carry on the bus exchange of data each time, it must be very valuable. In this case, there is no harm in considering adopting FIFO among data converter and DSP. Once FIFO reaches certain level and cuts off DSP promptly, is up to certain amounts of data words to finish in one step and transmit, this reduces the expenses that buses changed greatly.
Choose the accurate data pattern data converter to adopt different forms to the used data to the variable. Some use normal binary (namely unsigned binary scale) Data pattern, some adopt the data pattern of binary scale with symbol, this is complicated place of the question. If there are one and 12 data converters, then in case of binary data of tape symbol, how to use is a question. Sign bit occupy most important position, " 11 " Location (start bit of here " 0" Location) . If entrust " C " to this data word The variable, the width is " 16 " The location, assume " C " Sign bit" 15" . If the figure read from the converter is negative, then DSP does not discriminate it as negative value, because of the bit position mistake of the symbol. How to solve this problem? The first kind of method is to carry on the displacement of data while reading data fetch. However, this is possible while only reading data fetch in CPU, because DMA control device can not carry on the displacement of data during transmission. Another method is to move the data to the accurate position in the cycle after the data block is totally transmitted. But this must use CPU, and require extra MIPS. Change of converter connect, " 11" Location connect data always collinear " 15 " to DSP just The location, then sign bit just lies in the accurate position from the moment that first, this can realize the transmission based on DMA, and needn't carry on the displacement of data again either.
Guarantee what is dealt with is correct data now, data login, the data word is stored in the array, the data are suitable too in magnitude, then begin the processing data, but not obtained the anticipated result, need at this moment to think finally what's happened. Should check the cache of DSP at first, DMA transmit data launch cache while entering the memorizer, in this case, cache will probably keep the old data copied, and use them in the algorithm works. If this kind of problem happens, on the issue that must notice the associativity and deposit of cache removing, or store the new machine format cache area and fail. In this way, can guarantee the data that CPU deals with are the newest data transmitted after finishing.
It is apt to lose the key word while debugging embedded system to be if should be assigned by C language programming, after adopting the variable to inquire about the state of the peripheral hardware, find CPU used variable value is Improper, will think soon at this moment where on earth to go wrong. See this following structure first: unsigned int *pControl = (unsigned int *) 0x00COFFEE; file: //Wrong while (*pControl == 0); file: //Wait for one *pControl external incident here to point to a peripheral hardware. Circulate through while, expect EOC can be from " 0 " Change into " 1" . But in most cases, I'm afraid all the time that has waited, because the compiler thinks its already complete control variable and and its associated memorizer, only once of content of memory location that loaded *pControl points to, will carry on cycle test to it. But the problem lies in, because will not read the memorizer content again, can't finish circulating. The method to solve this problem is to revise the statement of *pControl, notifying its memory location pointed to of the compiler can be revised by the external incident, and must all be loaded again while using this variable each time, u.i.: volatile unsigned int *pControl = (unsigned int *) 0x00COFFEE; file: //Correct while (*pControl == 0); file: //Wait for a external incident
Guarantee, sample equidistance, punish sampled data in frequency domain, refer to a bit then: Not all converters start one's own time base changed newly. In this case, should adopt external time base or DSP to make the hour hand (timer pin) .
