SEEQC, NQCC Announce Digital Interfaces for QEC with NVIDIA
NVIDIA, SEEQC, and NQCC Launch Innovative Digital Interfaces for Scalable Quantum Computing
In a groundbreaking alliance, SEEQC, the UK's National Quantum Computing Centre (NQCC), and NVIDIA presented the first digital interfaces system connecting quantum computers to supercomputing gear. The ability to scale Quantum Error Correction (QEC), a prerequisite for large-scale, fault-tolerant quantum computers, is a major breakthrough.
The new system at the NQCC uses GPU-accelerated NVIDIA CUDA-Q decoders and SEEQC's digital quantum-classical interface. This all-digital method is meant to meet quantum computers' massive data throughput. The achievement enables large-scale, energy-efficient, quantum-enhanced AI and positions the UK as a leader in quantum and HPC convergence.
Error Correction Challenge Solution
Quantum bits, or qubits, are brittle and susceptible to environmental interference, causing computation failures. To build effective, large-scale quantum computers, these faults must be fixed in real time during computations. The requirement to analyse massive amounts of data with low latency has slowed progress.
“The secret to overcoming the decoding challenge is closely integrating quantum processors with cutting-edge AI supercomputing,” said NVIDIA Group Product Manager for quantum computing Sam Stanwyck.
This issue is resolved by the partnership's new system. The quantum processing unit (QPU) to GPU data throughput is 1,000 times faster with SEEQC's digital interface architecture than with analogue systems. This reduces data from terabits to gigabits per second without compromising speed.
In a statement, SEEQC CEO John Levy stated that their interface system's low latency and throughput efficiency enable quantum computing and GPUs to be more powerful. Energy efficiency allows heterogeneous computing without nuclear power and scalable, quantum-enhanced AI.
Combine Quantum and Classical Computing
The talk promotes heterogeneous computing, which combines classical and quantum systems. SEEQC's in-house Single Flux Quantum (SFQ) logic technology connects quantum and conventional components digitally, chip-based. This approach works with photonic, trapped ion, and superconducting quantum computing.
According to NQCC Director Michael Cuthbert, “realizing practical, scalable quantum error correction requires the integration of HPC and quantum computing.” Hosting the system at the NQCC lets the researchers show off the technology's wide interoperability and integrate it with cutting-edge HPC capabilities.
Chip-to-chip integration of a quantum processor and NVIDIA's Grace Hopper Superchip will create a powerful and scalable computing platform. It helps SEEQC build a full-stack architecture for hybrid quantum AI and machine learning applications and advance NVIDIA CUDA Quantum. SEEQC's earlier digital interface protocol presentation at NVIDIA's GTC conference is expanded.
With this relationship, SEEQC and NVIDIA are establishing the groundwork for enterprise-grade quantum computing, according to BCG quantum computing research lead Jean-François Bobier. Low latency unlocks much of quantum computing's benefits in scalable applications and error correction.
NVIDIA, NQCC, and SEEQC achieved quantum computing success. These scientists created the first digital interface device to connect quantum computers to supercomputing hardware for scalable Quantum Error Correction (QEC). Combining NVIDIA's CUDA-Q GPU decoders with SEEQC's digital quantum-classical interface for real-time, ultra-low latency error correction increases data flow efficiency by 1,000x over analogue methods.
This discovery at the NQCC is a key step towards heterogeneous computing and energy-efficient, quantum-enhanced AI by addressing the huge data needs of sensitive quantum systems. The system's success depends on processing terabits of quantum data down to gigabits per second without performance degradation, a major step towards fault-tolerant quantum computers.
