Synopsys releases DESIGN COMPILER 2007 to raise production efficiency and IC characteristic
Synopsys has released the latest edition of DESIGN Compiler comprehensive solutions - -Design Compiler 2007. The redaction has expanded topological technology, in order to adopt advanced low power consumption and test with higher speed the technical design disappears, help the designer to raise production efficiency and IC characteristic.
Topological technology can help the designer to assess the power consumption of the chip in the comprehensive course correctly, designing solving all power consumption problems in early days. In addition, also support Design Compiler 2007 test compression technique of China and Singapore, while realizing high quality test, reduce testing time and test over 100 times of data bulk, and it is congested to reduce the possible routing that the follow-up physical implementation phase brings because of the test circuit.
Hisilicon designs manager Huang Tao to show: "Adopt topological technology, performance predication and physics at comprehensive stage realize consequential conformance keeps within 5% of the deviation areas. Design Compiler 2007 can save chip area 5% on average while realizing the goal of high requirement characteristic that the communication is designed. One that is with overall arrangement is closely linked to guarantee the remarkable characteristic, this is exactly that a artificer introduces the competitive products to the market fast to need. "
Topological technology makes the result that synthetic realization result and physics realize have close conformance, this has been avoided repeatedly while realizing and designing dawdling between RTL synthesizing and physical layout in the convergence procedure. Design Compiler and Galaxy? Design the physical design solution of the platform to share technology and framework, can realize unanimous and high predictability of RTL to GDSII course.
Cypress data communication section is designed to the director Don Smith to show: "Cypress once met the conflicting test target, we needed at that time to realize that test coverage high, and test equipment of us lag behind relatively, can use pin and definite memorizer while being few only. We have assessed the adaptation sweep test compression technique of Synopsys, and disposed to in our procedure during less than one day. According to the result received, we are sure that can utilize existing test equipment framework, offer the most high-quality products. "
Design Compiler 2007 has adopted the comprehensive technology of multiple innovation, such as the adaptation retiming and power consumption drive the door control clock, characteristic the edition raises by 8% on average comparatively, the area is reduced by 4%, the power consumption is reduced by 5%. In addition, Synopsys Formality? Measure solution, strengthen, can prove technology the independently, completely equivalently, so the artificer, without casting out proving that can realize more high characteristic.