#microblaze

[microblaze]

ดับกลิ่นเหม็นทันทีที่ใช้

ด้วนจุลินทรีย์เข้มข้นของแท้นำเข้าจากอเมริกา ไมโครเบลส

Micro-Blaze official shop

สั่งซื้อที่นี่

รับส่วนลด สุดพิเศษ

ฟาร์มหมู ฟาร์มไก่ เนื้อ ไข่

ฟาร์มแพะ,วัว,เป็ด,นก,แกะ

แพะ ลำปาง ฟาร์มแพะแสนสุข

ฟาร์มสดใส ไก่งวง เพชรบูรณ์

พี.เค. ฟาร์ม

ฟาร์มเลี้ยงสัตว์ และอุตสาหกรรม อื่นๆ

ฟาร์มหมูรายย่อยภาคอีสาน

คลิ๊ก รับส่วนลด view: | https://s.lazada.co.th/s.C8Q43

[nettimelogic]

OPC UA server on a FPGA using open62541

Overview

Open Platform Communications Unified Architecture (OPC-UA - IEC62541) is a standardized platform-independent architecture which provides a service-based data exchange. In combination with TSN it allows new possibilities when it comes to high interoperability and deterministic communication.

Based on the open62541 implementation the following steps show how everything has to be setup to get it up and running on a FPGA (Artix7 with MicroBlaze). In combination with NetTimeLogic’s complete FPGA based TSN solution you get the full solution for industrial communication 4.0.

The example FPGA project and the application are available here:

https://github.com/NetTimeLogic/opcua

The open62541 implementation is available here:

https://github.com/open62541/open62541

Introduction

It is not straight forward to get the open62541 OPC UA stack up and running on an embedded system even if FreeRTOS and lwip is supported. The following implementation description is based on the open62541 documentation which describes how to build the library and how to implement a basic OPC UA server. The application creates an OPC UA server thread which is running under FreeRTOS with lwip.

The FPGA use a MicroBlaze softcore with DDR3, Axi Ethernet Lite, Axi Uart Lite AXI GPIO and AXI Timer. As hardware an Arty A7-100T development board from DIGILENT is used.

Required tools

To build the full project, the following tools are required:

Xilinx Vivado 2019.1

Xilinx SDK 2019.1

CMAKE (Python 2.7.x or 3.x)

UA Expert

BSP adjustments for LWIP

Open62541 supports “freertosLWIP” as an architecture. In that case it uses the libraries of the target device which are the ones of the BSP in Xilinx SDK.

To be able to compile the open62541 library some adjustments for the lwipopts.h file are needed:

Line 10-19 https://github.com/open62541/open62541/blob/master/arch/common/ua_lwip.h

Since this file is managed by the BSP in Xilinx SDK, manual modifications are overwritten when the BSP is generated. With the following workaround, it is possible to add the additional defines over the BSP setting GUI.

1. Go to: C:\Xilinx\SDK\2019.1\data\embeddedsw\ThirdParty\sw_services\lwip211_v1_0\data

2. Open the lwip211.tcl

3. Search the proc generate_lwip_opts {libhandle} and go to the end of this procedure

4. Add before the line puts $lwipopts_fd "\#endif" the following code:

#OPEN62541 implementation

set open62541_impl  [expr [common::get_property CONFIG.open62541_impl $libhandle] == true]

if {$open62541_impl} {

      puts $lwipopts_fd "\#define LWIP_COMPAT_SOCKETS 0"

      puts $lwipopts_fd "\#define LWIP_SOCKET 1"

      puts $lwipopts_fd "\#define LWIP_DNS 1"

      puts $lwipopts_fd "\#define SO_REUSE 1"

      puts $lwipopts_fd "\#define LWIP_TIMEVAL_PRIVATE 0"

      puts $lwipopts_fd ""

}

5. Save the file

6. Open the file lwip211.mld

7.Add the new Parameter e.g. at line 47:

PARAM name = open62541_impl, desc = "Used as an open62541 implementation?", type = bool, default = false;}

8.Save the file

9. Restart Xilinx SDK

After this change and a restart of Xilinx SDK the new option will be visible in the BSP settings GUI of the lwip.

Design preparation

Before everything is ready to build the open62541 library, the implemented FPGA design from Xilinx Vivado and a software application project in Xilinx SDK is needed. In this example project a MicroBlaze design with DDR3 is used (unfortunately the application does not fit into the available block RAM).

Vivado

The Vivado project can be created with the available tcl script. By running the implementation of the Vivado project the bitstream can be created. With File->Export->Export Hardware the hardware definition can be created.

File->Launch SDK starts the SDK.

Xilin SDK

In Xilinx SDK a new empty Application Project with the OS Platform “freertos10_xilinx” can be created.

File->New->Application Project.

After the project is created some adjustments in the OpcServer_bsp are needed

Select lwip211 as supported libraries

Go to the lwip211 and adjust following parameter:

  api_mode = socket_API

 open62541_impl = true

Go to the freertos20_xilinx and adjust the following parameters:

Check_for_stack_overflow = 1

total_heap_size = 2097152

Re-generate BSP sources

The environment is now ready to start with CMake.

CMake

The easiest way is to work with the CMake GUI. Later it can be used in Xilinx SDK.

CMake for open62541 is used with following adjustment:

UA_ENABLE_AMALGAMATION = ON

UA_ENABLE_HARDENING = OFF

UA_ARCH_EXTRA_INCLUDES = <path to microblaze/include>

UA_ARCH_REMOVE_FLAGS = -Wpedantic -Wno-static-in-inline -Wredundant-decls

CMAKE_C_FLAGS = -Wno-error=format= -mlittle-endian -DconfigUSE_PORT_OPTIMISED_TASK_SELECTION=0 -DconfigAPPLICATION_ALLOCATED_HEAP=3 -DUA_ARCHITECTURE_FREERTOSLWIP

UA_LOGLEVEL = 100 (optional for debugging)

1.      Start the CMake GUI

2.    Select the correct source code path where the open62541 GIT repository is located and define the path where you want to build the binaries:

3.    Click Configure:

4.    Select the CMake file which defines the compilation toolchain and other settings:

5.    Click again on Configure and after that on Generate

6.    The Unix Makefiles are now ready  and can be added Xilinx SDK workspace:

File->Open Projects from File system

7.    Now it should be possible to generate the open62541.c/h file in Xilinx SDK.

Make Target->all

8.      The workspace should have now following structure:

Creating the OPC UA server application

C/C++ Build settings

For a compilation without errors some adjustments in the application project Build settings are required.

1.   Add the symbol for UA_ARCHITECTURE_FREERTOSLWIP

2.   Add the open62541 build directory as include path

3.   Add the open62541 build directory as library search path

4.   Link the folder to the source location of open62541.c/h

5.    Add an exclusion pattern that only the open62541.c/h are used:

Linker script

The linker script for our OPC UA server application needs some small adjustments.

With Xilinx->Generate linker script a new lscript.ld with following settings can be created:

Heap Size: (min) 1MB

Stack Size: (min) 1MB

 Now the application project should be ready for a successful compilation.

OPC UA Server app

The complate Workspace is here available:

https://github.com/NetTimeLogic/opcua/tree/master/Src/Sdk_workspace

In Xilinx SDK the source file OpcServer.c can be imported to the OpcServer application project.

The thread stack size is defined with 4096 it might be possible that the application is not running properly with other values. However, the hook functions for MallocFailed or StackOverflow might be helpful.

In a first step the network initialization is done. This includes auto negotiation, ip configuration, interface binding and starting the lwip receive thread. After that the opcua thread gets started.

Important for a working server is the configuration and especially the buffer size of the network layer. With the following settings, the server was running without any problems: 

config->networkLayers->localConnectionConfig.recvBufferSize = 32768;   config->networkLayers->localConnectionConfig.sendBufferSize = 32768;   config->networkLayers->localConnectionConfig.maxMessageSize = 32768;

Before the server is started an object and a variable are added to the server. Additionally, a callback for the variable is configured, which allows to control the LEDs on the ArtyA7 board by an OPC client. After that the server gets started and runs until the running variable is set to false (never in this case).

Connecting to the OPC UA Server

After a successful implementation of the MicroBlaze FPGA design, building the open62541 library and compiling the OPC UA server application everything is ready.

The Arty A7 board should be connected to the PC over USB and the RJ45 is connected to a network interface adapter.

1.    Open a serial terminal for the debug print out (baud rate: 115200)

2.    Loading the bitstream (from Vivado or SDK)

3.    Run the Application (from SDK)

4.    If the application has successfully started, in the serial terminal following text is printed out:

5.    Start UaExpert

6.    Add the server via “Custom Discovery” with the configured open62541 hostname

7.    Expand the added server to add the connection. In the serial terminal you get already some information that a new connection over TCP was detected

8.    After a successful connection in UaExpert the defined object a variable are visible.

9.      The variable LED can now be added to the Data Access View via drag & drop

10.    By changing the boolean value of the variable, the LEDs on the ArtyA7 can be switched on /off.

Summary

To get an open62541 server running on a MicroBlaze softcore following adjustments are needed:

Add the defines in the lwip BSP for lwipopts.h:

#define LWIP_COMPAT_SOCKETS 0

#define LWIP_SOCKET 1

#define LWIP_DNS 1

#define SO_REUSE 1

#define LWIP_TIMEVAL_PRIVATE 0

Adjust the BSP settings for lwip:

api_mode = socket_API

open62541_impl = true

Adjust the BSP settings for FreeRTOS:

Check_for_stack_overflow = 1

total_heap_size = 2097152

Adjust CMake options for open62541:

UA_ENABLE_AMALGAMATION = ON

UA_ENABLE_HARDENING = OFF

UA_ARCH_EXTRA_INCLUDES = <path to microblaze/include>

UA_ARCH_REMOVE_FLAGS =    -Wpedantic -Wno-static-in-inline

-Wredundant-decls

CMAKE_C_FLAGS =  -Wno-error=format= -mlittle-endian

-DconfigUSE_PORT_OPTIMISED_TASK_SELECTION=0

-DconfigAPPLICATION_ALLOCATED_HEAP=3

-DUA_ARCHITECTURE_FREERTOSLWIP

UA_LOGLEVEL = 100 (optional for debugging)

Generate a linker script with at least: 1MB heap and 1MB stack

Adjust the C/C++ build settings / include sources/libraries

Define the thread stack size to 4096

Adjust the buffer size of the server config:

config->networkLayers->localConnectionConfig.recvBufferSize = 32768;

config->networkLayers->localConnectionConfig.sendBufferSize = 32768;

config->networkLayers->localConnectionConfig.maxMessageSize = 32768;

[utf2005]

Yes.  YES.

[gruegke-blog]

The fight of FPGA soft core lighted the innovative passion

Xilinx go on the staging to his MicroBlaze embedded processor kernel will it be autumn 2007, add a memory Administrative unit (MMU) Select, it is high grade and supporting the operating system of the fictitious memory to offer for processor of 32bit. The developer can also only use a simpler memory protected location (MPU) Or totally give up the memory management supervising.

The first full-function operating system which faces new MicroBlaze v7 already released at present is BlueCat Linux of Lynuxworks Company. Up till now, MicroBlaze processor only limited to supporting simpler embedded operating system, these systems are unable to support the fictitious memory or memory to protect. Have possessed MMU or after MPU selects, MicroBlaze v7 is suitable for the range more widely and needing embedded application of more high safety and reliability.

MicroBlaze v7 has another innovative approach, the new order can offer more quick floating point characteristic, and can improve it with the coprocessor and customize I/O characteristic between the logical circuits. In addition Xilinx enable its satisfied newest CoreConnect processor local bus line (PLB) the intersection of CoreConnect and the intersection of interface and staging already V4.6 norm, guarantees to have more quick connection speeds between peripheral hardware on processor and one.

Strong memory supervisory function

Since introducing the soft processor MicroBlaze in 2001, Xilinx has been carrying on constant improvement to it all the time. Two years ago, Xilinx began to offer a kind of FPU to select. In 2006, Xilinx lengthened the assembly line of its order, thus permitted to adopt more high clock speed. At earlier time in 2007, Xlinx released MicroBlaze v6, added the miscellaneous enhancement measure of drib. Now, Xilinx introduce the first class the intersection of memory and supervisory function through MicroBlaze v7, this expand the intersection of MicroBlaze and appropriate embedded applied range notably.

Certainly, a lot of embedded systems do not need so high lateral memory management, so MicroBlaze MMU is a kind of option function. Another kind of alternative method is to implement MPU, it can protect the memory in case of not having fictitious memory and address translation. MPU is suitable for protecting procedure storage area from receiving other procedure accidents or invading embedded systems of evil intention in those. And another option, namely implement the modal execution of privilege under the condition of having no protecting or fictitious memory of memory. Under the privileged mode, only the operating system or utility program with preferential privilege can carry out those orders about systematic safety.

Table 1 shows every kind of option (MMU, MPU or privilege carry out preferably) How to influence processor scale after synthesizing, it weighs yardstick, realize these functions in the programmable logic framework of FPGA and look up table that must increase Quantity. While realizing the privileged mode alone, there is few required LUT, the miscellaneous option needs to carry on more careful consideration in advance. Especially, MMU probably needs 1 000 LUTs, probably accounts for a function to dispose nuclear 1/3 in complete MicroBlaze v7.

Manage the scale of selecting in 1 3 kinds of MicroBlaze v7 memory of table

Complete MMU manages part of the reason to select as memory of maximum, it needs to change the look-aside buffer (TLB) To finish some contents of the look up table of address conversion of the fictitious - physical memory.

MicroBlaze v7 has integrated TLB of a piece of 64 clauses and subclauses. The dashpot that for this supplementary software management, has offered the shade clauses and subclauses used for order memory pages and data memory page. Shade clauses and subclauses quantity can from user-defined: The quantity of clauses and subclauses of buffering the order can be 1, 2, 4 or 8, and it is the same to buffer the machine format clauses and subclauses and count as it. The processor can be automatic to manage the clauses and subclauses of shade, thus prevent system disappointment (thrashing) Appearance. The dimensional range of the memory page is 1kB- 16MB, and can use various page size in admixture. After adopting the address mode that the significiant figure is 32bit, MicroBlaze v7 can carry on addressing in reaching 4GB memory.

MicroBlaze MMU imitates MMU in some IBM Power 405 processor to design. Because some Virtex series FPGA integrate one Power 405 kernel that strengthen before the this, its speed should be faster than a synthesis to MicroBlaze processor in this framework far. It can bring several advantages to MicroBlaze v7 to adopt similar MMU. First of all, programming person it transplants MicroBlaze to to be more light based on fictitious memory operating system from the intersection of Power and framework in course of framework. Second, developer can for 405 collocate to stand up one or more of the intersection of MicroBlaze and kernel with one Power easily, form a polykaryon to design by way of disposition of the shared drive. Third, Xilinx may integrate newer Power kernel in its FPGA through cooperating with IBM in the future.

More quick CoreConnect bus

CoreConnect is that IBM used the bus line in one of SoC, it was developed successfully in 1999. Though the main intention that IBM creates CoreConnect is serving for one's own Power framework processor, but anyone can be regarded CoreConnect as a kind of very synthetic intellectual property right (IP) freely The permission that the module used, it is not limited to a certain particular CPU framework. In the past 8 years, the soft IP manufacturer had already developed a lot of respectively and CoreConnect has been compatible, can release having kernels outside of the licence. An only a gets and has AMBA that the bus framework is ARM as slice of extensive support.

[vovsis-blog]

Comparable to fairy and think and introduce the new MICROBLAZE embedded kit

Can make embedded the intersection of system design and rapid start The low-cost kit includes Platform Studio integrated design environment comparable to fairy to think and repeatly obtain the special honours, Spartan-3E is embedded to develop board and flexible 32-bit microcomputer MicroBlaze soft processor Comparable to fairy and think in the company and claim to put out the MicroBlaze