High-accuracy MOSFET design tactics
As personal computer industry is advanced towards the working current for 1V key voltage of 200A, in order to meet those demands, and offer the required method of new device of the tailor for this market, the semi-conductive trade is suffering the huge pressure. In the past, so long as MOSFET design engineer improved its characteristic gradually and met market's demands and usually obtained the satisfactory result.
Now, the requirement that they face deviates from the passive response or voluntarily proactive design method at all, this kind of method should let them offer larger electric current, more high efficiency and smaller area of position occupied in order to meet the demand increased day by day, thus tackle the challenge for DC-DC converter increasingly small volume resources to bring. For this reason, it has surgery type precision design methods that this text puts forward a here, to design MOSFET for demand of this market. Such basic change is proved to be proper, because the market is big, it is enough to prove the required cost is proper, and can offer the solution of meeting market demand very much.
Fig. 1: Boost converter.
MOSFET design method
The converter is that a PC trade is the selected topological structure of DC-DC converter to step up synchronously, and is widely used in other markets of telecommunications. We will only consider in this text this kind is topological, but the same method may even be suitable for other topological. We will try to derive and calculate the equation for the area of MOSFET bare chip of optimizing according to two factors.
1. Its role in circuit is a switch MOSFET of the power or synchronous rectifier;
2. General loss correlated to such special MOSFET.
The immediate cause for choosing total loss as the determining factor is that the industry needs more high efficiency and lower loss. The area of the bare chip undergoes MOSFET of optimization, when used in its goal is employed - the switch MOSFET or synchronous rectifier -, can offer the minimum loss. Obviously, such an equation depends on special craft and use used for making the device the special device that this craft carries on is designed.
Through employing the parameter to linking up device area and physics, we can investigate the impact on difference of the device of these parameter, and in case of the best, we can design a kind of device according to employing the demand to be accurate, or in other words, a kind of MOSFET directed against special application. This kind of method makes the power semiconductor trades all produce the power device meeting the demands each time, and dispel the conjecture work in the design process, thus make development cycle shorter and the expenses are lower.
In order to simplify the equation that is derived, we restrict the calculation that loss to two kinds of predominant loss sources:
1. Conducting loss;
2. Trends or switching loss.
All the time, people have neglected the gate electrode to the capacitive charging and discharging between source between source and drain. Under the conditions of given 300KHz switching frequency and 12V input voltage, these two kinds of loss sources take very small percentage in the loss of the whole device. On the other hand, through introduce two the intersection of loss and source these, make, utilize Maple mathematics of software derive course to be more complicated really, it makes equations derived too complicated, it is difficult to study and employ the impact on device area of the parameter by utilizing it.
The crest MOSFET losses
The loss of letting us consider these two kinds of sources in the switch MOSFET: The first kind is conducting loss or ohmic loss, the second kind is dynamic loss. Conducting loss whether simple I2R x loss null cycle, and dynamic loss or switching loss open or close in the course from MOSFET because drain limited in voltage and flowing through it electric current. Lossing may be calculated by the following formula:
(1)
Among them: Tr and tf =Rise and fall time; Vin =Input voltage; ILoad =Load current; Fs =Switching frequency; RDSON = MOSFET on resistance; Δ PWM = Null cycle; Rpackage =Capsulate impedance;
In order to calculate tr and tf, we need to make to be following to suppose:
Tr ≈ tf
As to switch, consider gate electrode reach leak polar electric charge composition Qgd, because the gate electrode electric charge Qg does not work its magic in the switch only.
Among them: Qgd = Door or drain electric charge; Kd = Constant; Id = Door drive current on the threshold of the door; A = Area of the bare chip;
Replace (1) ,We get:
(2)
Fetch (2) -The first derivative of the area A- of the bare chip, we get:
(3)
Fetching the second derivative, we get:
(4)
Equation (4) It is straight, expressed as A solving (3) Will produce the minimum of a function. Solving A, we receive the minimum of the function Pdissipation:
(5)
And the area of bare chip of optimization may be calculated by the following formula:
(6)
Replace Δ PWM with Vout/Vin, and VDrive/Rg replaces ID, we get:
(7)
Because of VoutILoad = Output power =Pout
(8)
Attention: Aoptimum is proportional to directly Pout but inverse ratio is in Vin
Synchronous rectifier:
Utilizing identical treatment, we can derive the equation for directing the synchronous rectifier against:
(9)
Similarly, making can be shown to optimize the area of the bare chip by the following formula:
(10)
We take crest MOSFET as examples, the picture below 2 shows for the relation between area of bare chip of optimization at the time of different input voltages and load current. Investigate and discover carefully, when the input voltage turns 19V into to 5V, the area of the bare chip increases.
Fig. 2: The area of bare chip of optimization is a crest MOSFET function of the load current under different input voltage conditions.