28nm FD-SOI Industrial Solution - Overview of Silicon Proven Key Benefits
"28nm FD-SOI Industrial Solution - Overview of Silicon Proven Key Benefits. FDSOI/UTBB Technology Benefits, FDSOI Complete Solution. Demonstrated Reduced design effort for Full SoC porting. Same design flow as for 32/28nm LP
•Same design cycle time. Direct mapping of IPs + ECO
•Faster than rerunning synthesis
•Floorplan reuse. True concurrent engineering
•FDSOI product received before bulk version. 28FD Proven Excellent Core Energy efficiency. Same Perfs as 28LP with 200mV Less. SoC Cooler Demo. SOC Design, Design Solutions, Silicon Technologies. 28FD Devices Portfolio. Design Platform extended IP offer-Improved Memory Minimum Voltage. Vmin gain thanks to better mismatch on FDSOI devices (undoped channel) Design and Ips EcoSystem
•Conventional (bulk) design flow
•Cadence, Mentor, Synopsys,
•Apache, Atrenta. 4-terminals spice models available, from PSP
•Major simulators supported : Hspice, Eldo, Spectre
•Same low power design techniques than bulk. In addition :
•Optimized power switches
•Reverse & forward Dynamic body bias
•Digital IP suppliers ecosystem in place Synopsys, Cadence, ARM, ...
•Phys IP suppliers ecosystem : wide IP offering
•ST Technology R&D, ST divisions
•Cadence, eSilicon, Evatronics...
•Universities and research institutes
•access to 28FDSOI for prototyping and small series-CMP in Grenoble (site cmp.imag.fr)-link to CMP through VDEC in Japan, and CMC in Canada. 28nm Planar UTBB FD -SOI Roadmap. ST DESIGN PLATFORM IS AVAILABLE. Planar UTBB FD -SOI Enabling Moore’s Law with Planar Process & Design. FDSOI Technology Road-Map and Process Boosters. 14FDSOI Technology Features High Performance Logic. 14FDSOI offer •High performance, low power applications •Thin oxide devices : 2-Vts, poly biasing & FBB •Thick oxide devices : 2-Vts, multi voltage support •6T-SRAM bitcells:0.081um2, 0.089 um², 0.107um2 •Full suite of passive devices including high precision MOL resistor and MIM cap. 14FDSOI process features •UTBB substrate (BOx 20nm Si 6nm) •Hybridation(Mix SOI & bulk) for analogue •Si/SiGe channels for N & P •Gate first HK (HfO2) integration •Dual epi SiCP/SiGeB for transistor boost •NiSi •Local interconnect for standard cells density •90nm CPP, 64nm Mx •Up to 11 Cu metal levels •8 masks less than 20LPM for +20% speed @0.9V.
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