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Data Destruction Method-SSD in Military Applications

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For military applications, data security concerns military secrets or even decides the outcome of the war. Especially in modern warfare, on the one hand, countries go all out to develop more advanced and safer electronic systems, and on the other hand, they try every means to decode each other’s systems. And yet, as the data medium, the hard disks try all encryption methods to prevent being decrypted and meanwhile pay closely attention to quick erase or data destruction under various emergency environments.

Data Destruction Classification

In general, data destruction is divided into two types:

One is Logical Destruction which only destroys the data but not the physical chipsets. SSD is reusable after data-destructing or firmware re-implanting.

Logical Destruction normally executed by two mode: ① Quick Destruction (namely fast purge), to delete the data information quickly by pressing erase key; ② Data over-writing or filling which usually takes several hours depending on the SSD capacity. These data destruction methods can be implemented by software, but mostly by hardware.

Generally Quick Erase is not actually erasing data, thus it is risky at some level, but it is inevitable and important under urgent environment.

Another type is Physical Destruction with chipsets inside burned directly, that the data recovery is impossible in this way.

Physical Destruction generally utilizes the following methods: crushed by hammer or other heavy stuff, destructed by strong acid, destroyed by explosive or burned the chipsets by high voltage.

Approaches for Data Destruction

In general, both logical and physical data destruction can be implemented through specified Pin or a hardware key if the host system and SSD device unify the Pin definition.

It is necessary to set misoperation time for the destruction through hardware key, normally a few seconds before triggering the destruction function.

Physical destruction by high voltage is much more difficult than logical destruction, and the more difficult part is how to ensure every piece of NAND Flash chipsets being burned up. Theoretically, it can be easily realized by several methods to burn the chipsets one by one, while in view of practice, burning up one chipset usually takes long time and may not continue burning the next chipset thereafter or maybe there’s some chipsets failed to be burned up.

Destruction Standards

The data destruction standard is different from each country. Some require over-writing for 7 times while some others require for 4 times, and some countries regard deleting the encryption key as secure destruction. The security department in each country has different requirements for data destruction standards and methods, so just implement corresponding mechanism for SSD solutions.

Application Scenarios

I.Acceleration Sensing Physical Destruction SSD

This is an application in warcraft, the design purpose is to prevent military data leakage when the warcraft is shot down. To solve the data destruction in this case, the accelerometer could be inserted in SSD. When the craft start falling down, it would sense the acceleration and trigger the data destruction automatically when reaching the present threshold value to destruct the SSD physically. No need manual operation during the whole process. Even if the crashed warcraft is found, the internal military data information has vanished.

II.Remote Destruction

Remote Destruction is getting pretty common, even iPhone supprots remote data destruction and many SSD solutions also utilize a SIM card internally to implement the remote destruction function. Therefore the data destruction by methods of sending messages is quite “low” among present technologies.

For military applications especially outdoor ones, utilizing GPS (e.g. BeiDou in China) can also realize remote positioning and destruction, and more reliable. It requires authorization to usa GPS, navigation system is usually one-way communication which can only receive satellite signal but not send signal to satellite, the military can execute remote destruction through satellite after getting authorized.

Whether GPS or SIM Card, they have to solve the signal problem.

III.Automatic Destruction when leaving the specified location

Restrict the use of the disk in a certain area (e.g. inside the Command Post), the destruction program will start automatically when the computer is detected leaving out of the distance of the specified location.

IV.Physical Destruction continues after external Power Supply being cut off

When the external power supply is cut off during executing data destruction, SSD will continue to finish the process using the reserved power offered by built-in batteries or capacitors.

V.Unfinished Destruction continues after Retry Powering on the disk when the external power supply is cut off during the data destruction process, the destruction will be stopped, but it will continue the unfinished part after retrying powering on the SSD.

The disadvantage for this method is that there is a potential risk for the un-destructed data to be recovered if the enemy decodes data through disassembling the NAND Flash chips.

VI.Re-define Pin Assignment, SSD starts to destruct when connecting to a new device after leaving the original device

The SSD is bounded together with the client’s hardware, thus the SSD is irregular, and it will be burned when connected to other devices for decoding data if the enemy does’t know the pin definition.

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As the most important factor of test, logical approach is to define the workflow of the test process first, and then just adopt simple codes can get ideal conclusions. LSB (Least Significant Bit) and MSB (Most Significant Bit) are actually two bits in the same cell of a MLC NAND Flash, LSB is relative to Lower Page and MSB is associated to Upper Page. As the Lower Page is programmed first, the Upper Page has higher requirements for the voltage accuracy during programming. Programming the Upper Page is slow and inevitably causes influences or even errors to Lower Page. And in theory programming the Lower Page certainly has effects on the Upper Page. Two important questions have to be answered first for testing LSB and MSB: 1. How to figure out which is LSB and which is MSB. 2. How to test the influences on MSB by LSB program? And the vice versa. For the first question, some NAND Flash manufacturers give out which are the shared pages with a list in the datasheet, while some others don’t provide this. It is quite simple for those with the list, we can just follow the list to do the test. Shared Pages List provided by Nand Flash manufacturer:

And for those without such list, we can judge by testing the programming time for each page that the pages with shorter programming time are Lower Pages and longer time are Upper Pages. Suppose the NAND Flash manufacturer doesn’t provide the list of shared pages, there are two approaches to test the programming time for each page: One is test through the GUI of NFA100, and another is test through scripts. The script takes the advantage of handling all the other tests to avoid redundant steps.

Based on the above, the test flow chart is designed as follows:

Create a new.txt file, then just change .txt to .SSL as the suffix of NFA100 script, test script as follows (e.g.): ECCANA 0 VSET08 0 456789CF REPEAT 0000008 000003E8 BKERAS 0 0003 PGRDDM 0 0003 004 0300 PGRDDM 0 0003 004 RDMOVL $V08_0$ PGRDCP 0 003 004 0300 RANDOM 456789CF

PGRDDM 0 0003 004 RDMOVL $V08_0$ PGRDDM 0 0003 004 0300 PGRDEC 0 003 004 RANDOM 456789CF VADD08 0 00000001 FNECNT 1 blk0003.ect BKRDEC 0 0003 RDMOVL $V08_0$ Mutual impacts between LSB and MSB can be obtained rapidly by loading the script to NFA100, and of course the same approach can be adopted to test the interaction influences among the adjacent cells in a block, namely Program Disturb and Read Disturb.

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Data Destruction Patterns at Home and Abroad

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For military applications, data security concerns military secrets or even decides the outcome of the war. Especially in modern warfare, on the one hand, countries go all out to develop more advanced and safer electronic systems, and on the other hand, they try every means to decode each other’s systems. And yet, as the data medium, the hard disks try all encryption means to prevent being decrypted and meanwhile pay closely attention to quick erase or data destruction under various emergency environments.

Initial news of a contract between IBM and DARPA (Defense Advanced Research Project Agency) asks IBM to develop a “new class of electronics that the computers, sensors and other network devices could disappear automatically triggered by a signal sent from command”.When the commander sits in the command post with his feet up, he can just simply tap a button and the mobile phones, computers and all other devices in this controllable network could turn to ashes…

While technically this is obviously not just science fiction, we have got various weird demands and those technologies already realized are not lower than this at all.

Data Destruction Classification

In general, data destruction is divided into two types:

One is Logical Destruction which destroys the data only but not the physical chipsets, SSD is reusable just after destructing the data or re-implanting firmware.

Logical Destruction can be classified into two categories: one is Quick Destruction (namely Fast Purge), another one is over-writing which usually takes several hours depending on the SSD capacity. These data destruction methods can be implemented by software, but mostly by hardware.

Generally Quick Erase is not actually erasing data, thus it is risky at some level, but it is inevitable and important under urgent environments.

Another one is Physical Destruction with chipsets inside burned directly, data recovery is impossible in this way.

Physical Destruction generally utilizes the following means: Hammer or other heavy stuff for crush, strong acid for destruction, explosive to destroy it or high voltage to burn the chipsets.

Approaches for Data Destruction

In general, both logical and physical data destruction can be implemented through specified pin or a hardware button if the host system and SSD device unify the pin definition.

It is necessary to set misoperation time for the destruction through hardware button, normally a few seconds before triggering the destruction function.

Physical destruction by high voltage is much more difficult than logical destruction, and the more difficult part is how to ensure every piece of NAND flash chipset being burned up. Theoretically, it can be easily realized by several means to burn the chipsets one by one, while in view of practice, burning up one chipset usually takes long time and may not continue burning the next chipset thereafter or maybe there's some chipset failed to be burned up.

Destruction Standards

The data destruction standard in each country maybe different, some countries require over-writing for 7 times while some others require for 4 times, and some countries regard deleting the encryption key as secure destruction. The security department in each country has different requirements for data destruction standards and methods, so just implement corresponding mechanism for SSD solutions.

Application Scenarios

I. Acceleration Sensing Physical Destruction SSD

This is an application in some country’swarcraft, the design purpose is to prevent military data leaks when the warcraft is shot down. In such case, the pilot is probably dead, or even if he is still alive, then he can use the limited time for escape but no need to destruct the data by himself with sacrificing the chance of survival. When the craft starts falling down, the accelerometer in the SSD would sense the acceleration and triggers the data destruction automatically when reaching the preset threshold value to destruct the SSD physically, no need manual operation during the whole process. Even if the enemy finds the crashed warcraft, the internal military data has vanished.

II. Remote Destruction

Remote Destruction is getting pretty common, even iPhone support remote data destruction function and many SSD solutions also utilizes a SIM card internally to implement the remote destruction function. Therefore the data destruction by means of sending messages is quite “low”among present technologies.

For military applications especially outdoor ones, utilizing GPS (e.g.BeiDou in China) can also realize remote positioning and destruction, and more reliable. It requires authorization to use GPS, navigation system is usually one-way communication which can only receive satellite signal but not send signal to satellite, the military can execute remote destruction through satellite after getting authorized.

Whether it is GPS or SIM card, the signal problem is faced in both cases.

III. Automatic Destruction When Leaving the Specified Location

Restrict the use of the disk in a certain area (e.g. inside the Command Post), the destruction program will start automatically when the computer is detected leaving out of the distance of the specified location.

IV. Physical Destruction Continues after External Power Supply Being Cut off

When the external power supply is cut off during executing data destruction, SSD will continue to finish the process using the reserved power offered by built-in batteries or capacitors.

V. Unfinished Destruction Continues after Retry Powering on the Disk

When the external power supply is cut off during the data destruction process, the destruction will be stopped, but it will continue the unfinished part after retrying powering on the SSD.

The disadvantage for this method is that there is a potential risk for the un-destructed data to be recovered if the enemy decodes data through disassembling the NAND Flash chips.

VI. Re-Define Pin Assignment, SSD Starts Destruction When Connecting to a New Device after Leaving the Original Device

The SSD is bounded together with the client’s hardware, thus the SSD is irregular, and it will be burned when connected to other devices for decoding data if the enemy doesn’t know the pin definition.

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Upper Page and Lower Page

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According to the different characteristics of the Lower page and the Upper page to solve different problems, in practical applications will bring excellent results, such as: to enhance performance, greatly enhance the life, to solve the abnormal power failure reliability and so on. Some special applications may cause other losses, such as: to improve performance and life may need to sacrifice capacity, etc., but these trade choices are often more practical than the common sense.

The concepts of the Upper Page and Lower Page are not mentioned in the NAND Flash vendor's Datasheet. The Datasheet gives the general program time, which is the average time for Lower and Upper. In fact, the operation time of the Upper page The operation of the Lower Page is about 3-4 times (MLC). These conclusions can be intuitively seen through the NFA100-E:

The most direct test data (time unit: μs):

So, in the end the operation time is short called Upper page, or long operating time called Upper page? Is the Lower page a so-called "fast page" or "slow page"?

The answer is: Upper Page is a long operating time Page, also called "slow page"; Lower Page is a short operating time Page, also called "fast page". Why so, later analysis.

About LSB and MSB

Before talking about the Upper page and the Lower page, you must start with two words: LSB (Least significant bit least significant bit) and MSB (Mostsignificant bit most significant bit).

MSB refers to an n-bit binary number in the n-1 bit, with the highest weight 2 ^ (n-1), in the large order, MSB refers to the leftmost bit, LSB is the opposite.

Nand Flash initial state is "11", in this state, the left is 1 MSB, the right 1 is the LSB, so the process of Nand Flash Program, is the "11" MSB or LSB or two The program is "0" or continue to maintain the "1" state, thus, cell in fact there are four states, four state distribution corresponding to different Cell voltage:

11: Erase state;

10: Program 0 (LSB was program)

00: Program 0 (LSB and MSB are Program)

01: Program 0 (MSB was program)

Upper Page and Lower Page

So what is the relationship between LSB and MSB and upper page and lower page?

The vendor is doing this: the MSB and LSB a physical cell on the two bits were mapped to two different pages, then, LSB corresponds to the page is the Lower page, MSB corresponds to the page is the Upper page. The name of each generation of Nand Flash mapping methods are different, for example: 34nm and 25nm is not necessarily the same, 2D nand and 3D Nand are also different, the same is true, More sad reminder is that some manufacturers in the datasheet does not provide the corresponding table for the user query.

For example: page32 and page64, page75 and page138 are shared pages, beginning and ending of some pages (the number of uncertain, each vendor is different, 2D nand and 3D are different) have a special purpose, no distribution shared page.

Datasheet does not specify which page is, which is the Upper Page, which is the Lower Page, in fact, the small number is the Lower Page, the number is large Upper Page.

So why is the speed of the LowerPage fast, the upper page is slow? This is because, unlike the Lower page, the Upper Page in the Program, not only need its own threshold voltage, but also need to know the Lower Page threshold voltage distribution, specifically:

Nand Flash programming of a cell must be from the LSB is the corresponding lower page to start the implementation of programming, then, LSB will face two states:

1, if it is written "1", Cell threshold voltage will not change, still maintain the "erase" state;

2, if it is written "0", Vth will rise until the "10" or "00" required voltage value.

     LSB programming is completed before MSB is the Upper Page programming, the same:

1, if it is written "1", Vth will not change, still keep the erase state;

2, if it is written "0", then:

2.1 If the Lower page is "1", Vth will rise to "01";

2.2 If the Lower page is "0", it will rise to the "00" required voltage value;

Abnormal power-down effects:

As mentioned above, a physical cell is actually shared by two pages, then the problem is coming, since two bits in a cell are mapped to two different logical pages, then when one of the bits is Write operation (whether MSB or LSB), if the sudden power failure, then the data in this cell is bound to be lost, that is, the two pages of the data will be wrong. Therefore, the role of power protection is self-evident.

   Under normal circumstances, SSD will use tantalum capacitors or super capacitor to do power protection, the two have their own advantages and disadvantages, tantalum capacitors are more suitable for wide temperature environment, but the tantalum capacitor capacity is generally small, not suitable for large capacity SSD power protection , Super capacitor is not suitable for high and low temperature environment, more suitable for large capacity SSD power protection.

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Renice SSD Temperature Test Procedures Extreme Temperature Tolerance

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Temperature test of SSD products includes temp. cycle test and thermal shock test.

Note: Plenty of frost turned to water drops in the transition process from low temperature to high temperature. The water drops may easily caused short circuit of chip pins and thus burn the SSD. Therefore, reinforcement and waterproof treatment has to be done on tested SSDs.

Picture of a tested circuit board with frosting surface under -40°C

Temperature Cycle Test

The temperature cycle first set the temperature at -50°C and keep for 4 hours, then rising the temperature to +90°C, keep for 4 hours, next lower the temperature to -50°C to finish one cycle. Do multiple cycles in turn.

The standard of industrial-grade operation is -40°C to +85°C. Considering the temperature deviation of high-low temperature chamber and avoiding the inconsistent test result on customers’ side, Renice in-house test extend the temperature range at ±5°C based on standard.

Test Procedures

Lower the temperature to -50°C under the state of power-off, and keep it for 4 hours.

Note: Do not execute the low temperature test in power-on condition. Because the chipset itself generates the temperature above +20°C in power-on condition, it is normally easy to pass low temperature test. So getting the disks completely chilled is necessary before testing it in power-on state.

2. Power-on and run read/ write performance test on SSD, to compare the performance in normal temperature.

3. Aging test, to check if there is error created.

4. Power-cycling test.

5. Rising temperature up to +90°C and keep it for 4 hours. Contrary to the low-temperature test, the process of high-temperature test is done in power-on state to keep the inside temperature of chipset been in high state. And then executing the steps 2, 3 and 4 after 4 hours.

6. Repeat 10 times of high/ low temperature testing separately.

The test is judged as fail if any abnormity detected during the test.

In current market, there is common situation that screening the commercial-grade products for industrial-usage, while there could be risky. The screened products may have a high probability of failure in several temperature cycles. Besides, they cannot pass the strict extreme temperature test or pass the test one time but failed in next time.

Thermal Shock Test

The thermal shock means quick transition from low temperature to high temperature in few minutes (or customer time) and the high temperature to low temperature.

Normally the test starts from low temperature, which changes from -50°C to +90°C less in 3 minutes, or use the same method to start the test from high temperature.

During the temperature transition, Burin-test can be run all the time to inspect if there will be data comparison error during such quick temperature transition.

The specific test standard can refer to: GB/T 2423.34, IEC 60068-2-38, GJB150.5, etc..

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Renice SSD support Physical Destruction, Data Secure Erase and no way to recover, flash chips burn-out from xu jie on Vimeo.

Renice SSD support Physical Destruction, Data Secure Erase and no way to recover, flash chips burn-out

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Video: Renice SSD support Physical Destruction, Data Secure Erase and no way to recover, flash chips burn-out

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Amazing MRAM Performance: 4.6GB/s Read/Write Speed, but what frightens it?

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With the overwhelming advantages and high value, MRAM is being widely developed in laboratories all over the world.

The above product photo is our real shooting. Although with only 1GB density, the MRAM disk delivers breathtaking performance up to 4.6GB/S. And of course it will reach 6GB/s in the following stage, what a great expectation it brings to people?

Benchmark-Read/Write Speed：

MRAM vs. NAND flash

MRAM is a non-volatile random-access memory which works in a completely different mechanism comparing to NAND Flash and provide excellent characteristics:

1. With only the concepts of read and write, MRAM doesn’t need erase operation, the data stored can be covered directly, this is quite different to the annoying feature (erase before writing) of NAND flash, and therefore, the garbage collection mechanism is unnecessary to MRAM.

2. Write data in bits without having to consider page or block, there is no WAF (Write Amplification) for MRAM.

3. High speed, super long life, easy application, to put it simply, MRAM can be used as DDR.  

4. Non-volatile, no need to consider abnormal power fail handling, the practice of power failure protection is completely converted by MRAM and any kind of capacitor is unnecessary for reserving power.

5. In the aspect of data secure erase, the means of covering data by MRAM is much faster than NAND, and the simplest way to make the data unrecoverable is putting a big magnet on the surface of MRAM…  

6. ECC is still needed, the RBER of MRAM is 10(-10), and the disk error rate is 10(-16), just like enterprise HDD, thus ECC remains essential.

7. Natural radiation-hardened, perfectly solve the problem of single event upset in space application.

Limitations to MRAM

MRAM is so fantastic, while its limitations are obvious.

1. It is really too expensive, if I tell you the cost per GB in current condition is up to thousands of US dollars, can you believe it? That is to say, if you want a 500GB MRAM, you shall bring a Mercedes-Benz for exchange. And even the current NAND flash price is fluctuating and raised a lot, a commercial grade 500GB SSD can be bought with less than USD200 from Amazon.

2. The density is too small, the density of MRAM is still limited to 8MB and16MB, this greatly limits its application scenarios.

Reach me by email [email protected] or mobile [phone], or connect me on Wechat by scaning the following code.

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Why SSD failed after abnormal power-off?

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Considering the SSD must be based on FTL to realize the data transfer between logical address and physical address, if there happens abnormal power-off in case of normal operation (read/ program/erase), it may lead the loss of mapping table which has not finished updating and resulting in the SSD failed to be detected by host.

Meanwhile, to improve the read/write performance, SDRAM normally adopted as buffer on SSD board.The abnormal power-off also can cause the loss of data or updated mapping table which have not been written into NAND Flash from SDRAM.

Failure problem caused by abnormal power-off

1. SSD cannot be detected by OS once sudden power-off, it only be reusable after re-build mapping table or replanting.

2. Mass new bad block generated after repeatedly abnormal power-off.

The mechanism of new bad block generated is: when SSD cannot successfully read/ program or erase some blocks, such blocks would be marked as bad block. However, they are not real bad blocks, but a fault judgment by Controller due to abnormal power-off.

3. Loss of the data in SDRAM.

Typical method of power-failure protection

1. To protect the data integrity in SDRAM

This method must ensure all the data in SDRAM successfully be written into NAND Flash. In general, the capacity of SDRAM is set millesimal of total capacity of SSD. So for the SSD with small capacity, the data stored in SDRAM is limited, which could be realize write operation after power-off based on the power support of super-capacitor or tantalum capacitor. However, if the SSD with high-capacity like 8TB, the data needed to be written into NAND from SDRAM would be huge. In this condition, the suppliers have to solve below problems if still based on the super-capacitor or tantalum capacitor:

a. More tantalum capacitors demand. But in practice it is difficult to achieve due to the limitation of thickness, standard size and space of the board.

b. Even there are enough capacitors as power-supply, there leads another problem that SSD is unable to boot normally when execute “reboot”, which has to be powered-off for a while and then reboot again. Only discharged all of the tantalum capacity the SSD can be detected.

c. The tantalum or super capacitor will be aging after years of usage. When the power-supply of tantalum capacitor cannot reach the initial default value, there are also the potential risks of data loss or SSD failed to be detected after abnormal power-off.

2. Only save the data in SDRAM but not mapping table.

This method reduced the usage of SDRAM or tantalum capacitor. “Do not save the mapping table” does not mean the miss of mapping table, which only does not save the last updated mapping table.

When power-on again, SSD will find the new programmed data after last saved mapping table and then re-built the new mapping table. The disadvantage of this method is that it needs long-time to re-built the mapping table before SSD returning to normal use if without reasonable mechanism design setting.

To the SSD without SDRAM design, all of the data are written into NAND Flash directly. On this way, the data have not been written into NAND Flash will be marked as failure program and returned to host in abnormal power-off, then there is no extra data need to be saved. Therefore, for the applications need high reliability, the best design is without SDRAM. The only disadvantage is read/write performance not so fast. But in practice, most applications do not pursuit the best performance but enough performance with high reliability.

Test method and theory

In practical test, SSD should be tested in two conditions - as Master disk and Slave disk. Test as Master disk, the power-on/off operation is for PC, but as Slave disk, the power-on/off only for SSD.

a. Set 3000 cycles of abnormal power-off test separately for SSD in blank condition, filled with 25% data, 50% data, 85% data and full filled. The interval time of power-on and power-off is 3s.

The theory of test separately for SSD with different data capacity: The disk would run GC when SSD filled with certain data. GC means data movement. Each data move related to update of mapping table. The abnormal power-off happens in this period would lead the failure of SSDs.

b. Abnormal power-off test on SSD with common programming (write data into SSD)

To execute below 8 operations when write data file system in Windows:

From the above flow, we can see the process of writing data is also the process of updating mapping table. The abnormal power-off during this period still can affect the complete updating of mapping table.

c. Abnormal power-off happened during data erase process

Data erase implementation also has to execute above 8 operations in Windows. So the theory is same as file-building, the mapping table need to be updated.

d. Test 3000 cycles of abnormal power-off when SSD in read operation. Set the interval time of power-on/ power-off as 3s.

e. Test 3000 cycles of abnormal power-off during common startup and shutdown;

f. Test 3000 cycles of abnormal power-off in common boot the OS.

Refer to the industrial-grade or military-grade SSD, the above test should be run in high/low temperature environment.

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Detail the S.M.A.R.T of SSD

Original Chinese Version by Eric

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Before writing this article, we found during testing process that performance degradation occasionally happened to the SSD, and the S.M.A.R.T command was confirmed as the cause of this after study. This is seemingly not critical, however,it may bring serious consequence of losing data packets if the SSD is applied in those critical domains like data acquisition, while of course this bug is correctable,first let us look at the screenshot:

S.M.A.R.T Overview As the short for Self-Monitoring Analysis And Reporting Technology, S.M.A.R.T. can be read from its name with the function of fault alarm. The SSD health condition can be monitored and the parameter values can be fed back to the monitoring software or operation systems, in fact, most parameters are meaningful only for SSD engineers, the end users just need to focus on some key indexes, such as New Bad Blocks, Remaining Life and Erase Count, etc. S.M.A.R.T information of the SSD can be obtained through some common testing software:

SSD controller manufacturers can also provide corresponding tools:

Through the years of continuous improvements by HDD manufacturers, some S.M.A.R.T standards are formed, however, for SSD, most S.M.A.R.T parameters are user-defined, thus the parameters provided by every manufacturer may be different, but generally they refer to HDD S.M.A.R.T to set them. The S.M.A.R.T information of SSD is saved in specific areas assigned by firmware, it could be in the area of OP (Over Provisioning) or possibly any area chosen by the firmware engineers, or saved with an independent table. The S.M.A.R.T of SSD is not completely the same as of HDD, those common testing softwares which can be got from internet are designed based on HDD, SSD manufacturers usually make their own decisions to set S.M.A.R.T attributes according to the characteristics of NAND Flash. Definition of S.M.A.R.T Indexes 01 Raw Read Error Rate This index indicates the initial health condition of NAND Flash, the data values include correctable and uncorrectable errors. 09 Power-On Hours The unit of measurement is generally hour, it could be minute or second, which is defined by SSD manufacturer. Usually the time of all the three states of work, idle and sleep are counted, some SSD solutions exclude the time of sleep by enabling some power management functions. This parameter shows the accumulated power on time of the SSD, it is supposed to be 0 for a new SSD drive, while in fact the SSD manufacturers have already used for several or dozens of hundreds of hours during the testing process, it is just the parameter is resumed to be 0 by re-implanting firmware after the tests. 0C Power Cycle Count The data value of Power Cycle Count means the power on/off cycle count for the SSD, it is usually just a few times for a new drive. The power on/off for SSD is different to HDD, normally intense P/E cycle tests should be done for SSD, in addition, a large number of abnormal power off/on tests are required for military and industrial SSD to avoid the loss of mapping table or other unreliable factors which may be brought by abnormal power off. (3K to 10K abnormal power off/on cycle tests are done in Renice，but what users can read from the S.M.A.R.T reports is still a few power cycle count because the power cycle counts is cleared by re-implanting firmware after tests.) B8 Initial Bad Block Count Every NAND Flash has initial factory-marked bad blocks, the SSD firmware mark bad blocks by scanning 0xFF in the spare area of the first and the last page of each block, no mark of 0xFF expresses as bad block, bad blocks are managed by firmware uniformly and listed into bad block table. Initial Bad Block Count reflects the initial health condition of the SSD on a certain level, the larger number of initial bad blocks represents the worse initial health status. C3 Program Failure Block Count When Program Failure happens to a page, the block of this page will be marked as bad block, this sort of bad blocks is named as new bad blocks and listed into bad block management table. Every block has limited Program/Erase cycle, program failures or erase failures push the block into the bad block table for centralized management. For those domains with extremely high requirements for data security, a block with just one program failure, erase failure or read failure will be marked as bad block. C4 Erase Failure Block Count The explanation is similar to C3. C5 Read Failure Block Count The explanation is similar to C3. CA Total Count of Error bits from flash This count includes Program Disturb Error, Read Disturb Error, Erase Error, and total amount of correctable and uncorrectable error bits. This value may looks very high, especially for the SSD with weaker ECC capability. Taking the parameter of CB into account, we can have a rough estimate about the ECC capability of the SSD, the larger value indicates the weaker ECC capability. CB Total Count of Read Sectors with correctable bits errors This count just includes the amount of the corrected error bits, so the amount of uncorrectable error bits could be calculated by CA-CB, the bigger the difference between CA and CB, the weaker the error correction capability of the SSD is, and the shorter remaining life it represents. CD Maximum PE Count This parameter is set according to the specs in the datasheet of the NAND Flash, but in reality the PE cycle of NAND Flash is larger than that listed in datasheet, e.g. the provided value is 3,000, so the remaining life gets to 0 when the erase count reaches to 3,000, but the SSD actually remains in a healthy status. Hence this parameter is for reference of usage with the best insurance. CE Minimum Erase Count Maximum, Minimum and Average Erase Count describe the erase count of each block, the smaller the difference between the maximum and minimum value, the better the wear leveling algorithm it represents, the average value makes no sense. CF Maximum Erase Count Refer to CE for the corresponding definition. D0 Avage Erase Count Refer to CE for the corresponding definition. D1 Remaining Life (%) This index shows the remaining life of the SSD, we can guess from the description of CD that this parameter is just a reference value, it doesn’t represent the true remaining life of the SSD.