#on theme

[manjaro-official]

people online: I rent a proxy server to protect my privacy

people in real life: I just connected my Facebook account to my Venmo account for no reason and now I'm going to take a picture of you in public and post it with geolocation turned on

[coolmomvinyl]

I caught a glimpse of my 18 year old’s playlist she made during and after graduation. It was SOLID. 😯 I was hella surprised at how all over the place and yet thorough it was! And, how much she stole from me. Chip off the ol’ block! 😏 Here’s a sample:

[emuthefandomcollector]

Chica... What is your relationship with your Cupcake? :3 (like... you get along or nah?)

* For withered chica, Carl/Mr cupcake/her cupcake is unfortunately missing... Toy chica is so lucky for being able to keep Candy/her cupcake </3

[ofdarklands]

obligatory tacocat joke. in any case, relatable

girl you should DESTROY the dome. be FREE...

mitr'a, muttering: against my preference

WOE embarrassing purring and headbonks for the twins before they get on the boat. UNSKIPPABLE

kitby... 🥺

[verilog-official]

the genius (stupidity) behind the FPGA in my 6502 computer has almost everything to do with the clock.

basically, the FPGA has a 12mhz clock input, and an adjustable clock output which goes to the CPU.

with the 12mhz FPGA clock, the CPU can run up to 6mhz. however, since the 6502 uses a synchronous bus, all the other devices on the bus must be able to run at that speed as well. and, well, they can't.

my solution was to dynamically adjust the clocking for each peripheral on the bus when it's being accessed. the FPGA monitors the address bus, and when the CPU selects something that runs slower, such as the EEPROM, it halts the clock for a little bit until the EEPROM can catch up.

this allows me to put other stuff on the bus too, like the LCD controller. in the original Ben Eater design, the LCD was attached through the VIA (essentially a GPIO controller). since the nature of the LCD controller needing to constantly switch between reading and writing, this made a pretty sizable overhead. by putting it on the bus directly, not only do we free up 7 GPIO pins, we also significantly reduce the time it takes for something to be written to the screen.

there's was problem though; I plan on using the VIA's timer functionality which essentially just counts clock cycles. if the clock constantly changes speed, this number will be useless. so, the FPGA generates two clocks, a monotonic clock for the VIA, and a non-monotonic clock for everything else.

but the VIA also needs to be synced with the CPU in order for them to communicate. so, when the FPGA sees that the CPU wants to access the VIA, it synchronizes their clocks for a short moment, then essentially "connects" them together for one cycle, before reverting to their original clocks.

this way, the VIA can properly keep time, and the CPU can change its speed at any time. additionally, since the VIA has its own clock, you can adjust it independently and slow it down if you need to track long periods of time, or speed it up if you need more precision.

oh and I forgot to mention that the CPU can also adjust it's clock speed, but i don't think it would make much sense to do anything but the top speed.

[randombrowngirl]

Day three of spirit week

[strixhaven-star]

Put them all in the same deck. Make it work!