#riscv

[hannahmontanalinux-official]

Something something man with a RISC-V hammer something something

[msmissing-possum]

I really like RISC-V, but it looks like they keep putting NPU’s on the chips and marketing then as ai, but I think an open cpu that can run development software, etc. is more important right now, because not all RISC-V users are gonna be like OMG ITS AI I GOTTA GET THIS SBC!!!!

I saw a review of an sbc where 16GB of the 32GB was reserved for the NPU, and I think that’s bullshit

[verilog-official]

what is your CPU arch

x86

x86-64/amd64 (bleh)

arm/armel/armhf

arm64/aarch64

ia64 (can I marry you)

ppc/ppc64 (the ones in the old macs)

ppc64el (the new ppc ones I think)

RISCV (oo ily)

SPARC (are you insane)

other (PLEASE SPECIFY I SWEAR TO GOD)

I have no idea / results

Voting ended onMay 14, 2025

[andmaybegayer]

(doing something stupid) can you allocate an array at a specific address during compile time in C++. This system is Harva-actually wait the docs say this is almost a built in feature. Hang on.

Hell yes okay I have the thing I want working, you just have to. turn off memory protection and use the IRAM_ATTR thing. That's fine. I think I can make this work I'll just block out a couple kB of nops for my plugins. For a moment there I thought I was going to end up using WASM. I might still, WASM is infinitely safer than this. But this is very funny.

Love function pointer syntax. Makes perfect sense in that awful C way.

That array is just the -O0 implementation of an add in rv32. If you optimize it it's like two instructions but I just wanted to make sure I could execute more than one in a row. I think if you compile right with -fPIC/-fPIE and all that jazz you should just be able to dump that into RAM and execute. Since all your jumps will be relative?

[adafruit]

Desk of Ladyada - It's a RISC-V kinda weekend https://youtu.be/aC3vGKHRCBA

MMade progress on two RISC-V projects to finalize PCBs. We optimized the CH32v203g6 chip-based QT Py board by reducing it from a 4-layer to a 2-layer to cut costs, and integrated TinyUSB support for better Arduino IDE compatibility. We also advanced the Feather ESP32-C6 project, enhancing its deep sleep power efficiency and finalizing the USB Key 'Trinkey' for standalone gateways or sensors. Plus, we picked out a clear USB enclosure from Digi-Key for it.

[zipp-os-official]

Starting Production🎉🥂

ZippOS is an alternate operating system for stand alone “spacial computing” devices. The goal of this project is to provide end users, who at their own discression, void their warranties to replace pre-packaged software bundled with their hardware. As the lead developer of ZippOS, and as an end user of a “spacial computer”, I am displeased with the current operating software, and the decisions of parent companies that distribute these products are inheriently unstable, brown-nosing share holders and consumers, and completely unaligned with the end users. As these devices are marketed as computers, I want to provide software for said computers as a choice for the end-users who feel the same as I do.

ZippOS will be a lighter(get it?), faster booting operating system built from scratch with Rust-Lang and some ARM/RISC-V assembly code to replace both the BIOS (ZIOS) and the operating system. The operating system’s goal is to have the same user functionality and multimedia multi-instancing in a mixed reality setting, citing BeOS/HaikuOS as inspiration. This operating system will have security and graceful degradation as the main focus for user safety because the main enemy for ZippOS is the companies who made the stock software it replaces on the end-user’s spacial computer. Users can also enjoy various stimulating options for navigating the software (i.e. “rolodex” style hub menus, table-top program/application storefront, “grabbing” and “throwing” programs/screens to be cast/mirrored to and from realspace and cyberspace, etc). ZippOS is a project software operating system under development, and currently has no plans to publicly publish to the open net, nor are there any current plans to open-source the software.

[andmaybegayer]

okay if there are jumps something goes screwy. At present I am literally just copying the .text section of a .o file out so there's probably some label stuff. I might be able to pre-process the jumps to convert them? I was able to get a fizzbuzz to run but only because an O3 fizzbuzz doesn't actually have any branches. -O0 fizzbuzz got stuck.

[rubli25]

𝗥𝗜𝗦𝗖 𝗩 𝗠𝗮𝗿𝗸𝗲𝘁 𝗔𝗱𝘃𝗮𝗻𝗰𝗲𝘀 𝗮𝘀 𝗤𝘂𝗮𝗹𝗰𝗼𝗺𝗺 𝗘𝘅𝗽𝗮𝗻𝗱𝘀 𝗥𝗜𝗦𝗖 𝗩 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗜𝗻𝗻𝗼𝘃𝗮𝘁𝗶𝗼𝗻

Qualcomm is accelerating its RISC V strategy by expanding the adoption of open standard processor architectures across IoT, wearable, edge computing, and AI enabled devices. The initiative highlights the growing industry shift toward customizable, energy efficient, and scalable semiconductor solutions powered by RISC V technology.

By leveraging the open instruction set architecture, the company aims to deliver highly efficient processors that enhance performance, improve power efficiency, and enable greater design flexibility across IoT, wearable, industrial, and AI powered applications.

Semiconductor companies are investing in advanced RISC V cores, software ecosystems, development platforms, and strategic collaborations to accelerate innovation while reducing dependence on proprietary processor architectures.

𝗗𝗼𝘄𝗻𝗹𝗼𝗮𝗱 𝗙𝗥𝗘𝗘 𝗦𝗮𝗺𝗽𝗹𝗲

𝗞𝗲𝘆 𝗣𝗹𝗮𝘆𝗲𝗿𝘀

• Qualcomm continues expanding RISC V innovation across IoT, wearables, and edge computing applications.

• SiFive develops high performance RISC V processor IP for commercial and enterprise applications.

• Intel supports the RISC V ecosystem through strategic investments and semiconductor innovation.

• Andes Technology provides RISC V processor cores for embedded, AI, and industrial applications.

• Other major players include NVIDIA, Microchip Technology Inc., Synopsys Inc, Codasip, Imagination, and Esperanto Technologies, Inc.

𝗞𝗲𝘆 𝗧𝗮𝗸𝗲𝗮𝘄𝗮𝘆

Qualcomm's continued investment in RISC V technologies demonstrates the semiconductor industry's growing focus on open standard architectures, customizable processor design, and AI enabled computing. As adoption expands across embedded systems, automotive electronics, and intelligent devices, RISC V is expected to remain a key driver of innovation across the global semiconductor landscape.