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what is your CPU arch
x86
x86-64/amd64 (bleh)
arm/armel/armhf
arm64/aarch64
ia64 (can I marry you)
ppc/ppc64 (the ones in the old macs)
ppc64el (the new ppc ones I think)
RISCV (oo ily)
SPARC (are you insane)
other (PLEASE SPECIFY I SWEAR TO GOD)
I have no idea / results
(doing something stupid) can you allocate an array at a specific address during compile time in C++. This system is Harva-actually wait the docs say this is almost a built in feature. Hang on.
Hell yes okay I have the thing I want working, you just have to. turn off memory protection and use the IRAM_ATTR thing. That's fine. I think I can make this work I'll just block out a couple kB of nops for my plugins. For a moment there I thought I was going to end up using WASM. I might still, WASM is infinitely safer than this. But this is very funny.
Love function pointer syntax. Makes perfect sense in that awful C way.
That array is just the -O0 implementation of an add in rv32. If you optimize it it's like two instructions but I just wanted to make sure I could execute more than one in a row. I think if you compile right with -fPIC/-fPIE and all that jazz you should just be able to dump that into RAM and execute. Since all your jumps will be relative?
Desk of Ladyada - It's a RISC-V kinda weekend https://youtu.be/aC3vGKHRCBA
MMade progress on two RISC-V projects to finalize PCBs. We optimized the CH32v203g6 chip-based QT Py board by reducing it from a 4-layer to a 2-layer to cut costs, and integrated TinyUSB support for better Arduino IDE compatibility. We also advanced the Feather ESP32-C6 project, enhancing its deep sleep power efficiency and finalizing the USB Key 'Trinkey' for standalone gateways or sensors. Plus, we picked out a clear USB enclosure from Digi-Key for it.
Starting Production🎉🥂
ZippOS is an alternate operating system for stand alone “spacial computing” devices. The goal of this project is to provide end users, who at their own discression, void their warranties to replace pre-packaged software bundled with their hardware. As the lead developer of ZippOS, and as an end user of a “spacial computer”, I am displeased with the current operating software, and the decisions of parent companies that distribute these products are inheriently unstable, brown-nosing share holders and consumers, and completely unaligned with the end users. As these devices are marketed as computers, I want to provide software for said computers as a choice for the end-users who feel the same as I do.
ZippOS will be a lighter(get it?), faster booting operating system built from scratch with Rust-Lang and some ARM/RISC-V assembly code to replace both the BIOS (ZIOS) and the operating system. The operating system’s goal is to have the same user functionality and multimedia multi-instancing in a mixed reality setting, citing BeOS/HaikuOS as inspiration. This operating system will have security and graceful degradation as the main focus for user safety because the main enemy for ZippOS is the companies who made the stock software it replaces on the end-user’s spacial computer. Users can also enjoy various stimulating options for navigating the software (i.e. “rolodex” style hub menus, table-top program/application storefront, “grabbing” and “throwing” programs/screens to be cast/mirrored to and from realspace and cyberspace, etc). ZippOS is a project software operating system under development, and currently has no plans to publicly publish to the open net, nor are there any current plans to open-source the software.
okay if there are jumps something goes screwy. At present I am literally just copying the .text section of a .o file out so there's probably some label stuff. I might be able to pre-process the jumps to convert them? I was able to get a fizzbuzz to run but only because an O3 fizzbuzz doesn't actually have any branches. -O0 fizzbuzz got stuck.
I really like RISC-V, but it looks like they keep putting NPU’s on the chips and marketing then as ai, but I think an open cpu that can run development software, etc. is more important right now, because not all RISC-V users are gonna be like OMG ITS AI I GOTTA GET THIS SBC!!!!
I saw a review of an sbc where 16GB of the 32GB was reserved for the NPU, and I think that’s bullshit
The collaboration will leverage CEA-List’s RISC-V design expertise and CEA-Leti’s silicon photonics expertise to introduce high-bandwidth
CEA-Leti, CEA-List, and PSMC have joined forces to integrate RISC-V architectures with microLED-enabled silicon photonics—unlocking high-bandwidth, energy-efficient data communication for future computing systems. By combining customizable RISC-V processing with optical interconnects and advanced 3D chip stacking, this collaboration aims to overcome the limitations of traditional copper interconnects and power constraints, paving the way for scalable, high-performance AI solutions.
T2M High-Performance RISC-V IP Platform for Intelligent Embedded Computing
T2M provides a high-performance RISC-V IP platform delivering silicon-proven 32-bit and 64-bit processors for scalable embedded and application-class system-on-chip designs. Supporting configurable RV32 and RV64 architectures, the portfolio enables implementation across a wide spectrum of power and performance requirements. Designed for smart IoT systems, automotive electronics, industrial automation, consumer devices, and AI-enabled edge platforms, the cores integrate superscalar execution, vector acceleration, crypto processing, DSP capabilities, and configurable floating-point support.
The architecture incorporates hardware Root-of-Trust, advanced protection features, and ISO 26262 compliant functional safety up to ASIL-B and ASIL-D. Memory subsystems include tightly integrated storage with ECC reliability, complemented by scalable interrupt control and high-bandwidth AXI/AHB interfaces for efficient SoC integration. Supported by complete IP, subsystem, and development tool ecosystems and validated through production silicon, T2M RISC-V processors provide a robust foundation for next-generation embedded and compute-intensive semiconductor systems.
