#verilog

[techav]

An Update I Can Count On

I have the first signs of life from the new bus on my PikaPC prototype!

The logic ended up being quite a bit less complex than I expected, using only 32 macrocells. It's just simple state machine written in verilog.

I did have to rework my plan for bus cycle timing & handshaking to work around more quirks of the PPC403's weird bus interface, but it does work. This took me even further away from NuBus, which I originally started from. But if it works, it works …

I decided what I really needed to make sure things were working was a dead-simple test card. Nothing so complex as my DRAM card (which is what I want to tackle next) or even needing custom logic like my keyboard/mouse controller card.

So I threw together a card with a 74'574 register, a 74'139 decoder, and some LEDs. (So glad I decided to spin up some custom prototyping boards!) The idea being I can write a value to the register and it will show up on the LEDs.

This was a good idea. I was able to find I had miswired one signal and swapped a few more in my CPLD pin assignments. I also got to watch my logic run with a logic analyzer to see that the timing mostly worked as expected, but with still more weird quirks of the PPC403 I hadn't accounted for.

For the video at the top of this post I'm running a simple Forth program to count up from 0 to 15 and display the binary equivalent on the LEDs. It's a simple test representing another big milestone for this project. Now that I know my new bus controller works, I can start building more complex peripheral cards to go with it.

[electronicjester]

INTRO

I'm Anakin!! I'm 17 and Irish. He/him only please! I like jewelry, STEM and general fandom stuff.

Main interests currently: The Pitt, Better Call Saul, House MD, Will Wood, Willard, Portal 2, Of Montreal, The Magnetic Fields, Radiohead, Clowns, Teeline Shorthand, Inline skating, basic circuitry (digital logic/verilog mostly), JavaScript, Python, Ao3.

!! PLEASE INTERACT WITH ME I WILL GLADLY TALK TO ANYONE. SEND ME ASKS, DM ME, PULL UP TO MY HOUSE I DON'T CARE. WE ARE AUTOMATICALLY BEST FRIENDS IF YOU ACKNOWLEDGE ME !!

[balloonpup]

Upgrades

Static thought Verilog was joking when he suggested an upgrade.

"Yeah, sure, sign me up."

Oh, well, I'm sure Static will enjoy being a ying-o-gen.

By ShinyWark

[astelor]

Technically Finished

I went with the no serialization route and did not design a 8 bit output serialization module. (the accumulator have two RAM blocks and can output two 16 bit numbers at once) I did make a serialization module, but I realized it's up to that arbitrary specs (if the next module can accept 16*2 input, then that serialization is not necessary). So I just connect the accumulator outputs as they are.

and yeah, it's technically done. It's wack, it's bad, but it's done.

Welp I still need to write that paper :P

The total logic elements should be about 3000 more. Since I wrote quite a lot of unsafe code that raised all the warnings, some of the things that the IDE deemed "unnecessary" were omitted.

[verilog-official]

accidentally mistyped "shiftreg" as "shitreg" and decided to go with it

[assembly-official]

Assembly is not enough, i need to fuck my processor

VHDL or Verilog. I don't have any experience in Verilog, but have made some simple stuff on FPGAs with VHDL; it's pretty cool, but also quite frustrating since it's simultaneously the lowest level programming you'll probably ever do (as it is changing real hardware), but it's also quite abstract, so you don't really know what the compiler does; this makes fixing (heisen) bugs real tricky.

If you ment 'fuck my processor' more literally I recommend something with a LGA socket, because you will bend the pins of a PGA CPU. Also dry it off before reinserting it in your motherboard. I don't know how you'll get any real pleasure from it, but feel free to try!

[echobravofoxtrot]

The school bells are ringing! I am so looking forward to this year, especially now that things are starting to open up due to the availability of vaccines. I will be continuing in my role as an RA, but I now manage a floor comprised entirely of Computer Science and Engineering majors. The opportunity to tailor the residential curriculum specifically to topics in computing is going to be an amazing way to bring my own passions into the community. This year, I will also begin taking classes toward my master's degree in Computer Engineering, meaning that I will finish undergrad with half of my master's already out of the way!

Pictured in this post are some artifacts that I created this summer as a research assistant in a computing lab on campus. Our team is developing field programmable gate arrays (FPGAs) for defense applications. If you don't know, an FPGA is an integrated circuit that can be programmed to behave like any other circuit using a hardware description language like Verilog. They can be found in a host of devices you interact with every day (TVs, radios, cameras) as well as military-grade equipment like what I am working on. They are widely used due to their ease of programming, which allows for rapid and cost-effective development, as well as the ability to patch bugs without having to re-manufacture the circuitry.

In the lab, I maintain a custom toolchain that converts Verilog code into a bitstream that can be loaded onto our FPGA. At the moment, this is all happening in the context of a simulation, but by the end of the fall our little black box should come home from the factory and I can hold it in my hands! At that point, I will begin designing some circuit boards that make use of the device before it eventually makes its way onto a military drone or something of the sort.

I am very thankful for the experience I have gained so far, and I look forward to sharing more progress with you. Until next time!

[kangminyoo]

Netflix, please hire Dongheon